use that.
Signed-off-by: Timur Tabi ti...@freescale.com
---
We don't update p3060_ids.c because support for that SOC is going away.
arch/powerpc/cpu/mpc85xx/p2041_ids.c |6 +++---
arch/powerpc/cpu/mpc85xx/p3041_ids.c |8
arch/powerpc/cpu/mpc85xx/p4080_ids.c |6 +++---
arch
it so complicated. We already automagically upgrade the board from
NXID v0 to NXID v1. Now we automagically fix boards that have the CRC in
the wrong place.
Anyway, I don't see why it's so controversial. This code is only used on
a small number of Freescale reference boards.
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location (0xCC).
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offset
* to where it is in v0.
*/
if (e.version == 0)
crc_offset = 0x72;
So here we're reading the 'version' field before we validate the data,
because we need to check the version to know where the CRC is.
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that:
if ((e.version == NXID_VERSION) (crc != be32_to_cpup(crcp))) {
NXID_VERSION is equal to 1, so we only do the check for the old CRC if we
have a v1 EEPROM.
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EEPROM is filled with MAC addresses, and so we've reached the hard
limit of 31. We would need to switch to a new EEPROM device in order to
handle more, and none of the other information in the EEPROM is used by
U-Boot.
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The NXID v1 EEPROM format has the CRC at offset 0xFC, but for some reason it
was placed at address 0xCC instead. To retain compatibility with existing
boards, we check the CRC in the old location if necessary.
Signed-off-by: Timur Tabi ti...@freescale.com
---
board/freescale/common/sys_eeprom.c
it.
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it. It will read broken
EEPROMs and verify the CRC in the old location, and if you have re-save
the EEPROM, it will put the CRC in the right place.
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in sh_eth_config().
Same here, at least the core message Could not initialize PHY
I am saying that, just in a different way. phy startup failure means
the same as Could not initialize PHY, but the wording matches the rest
of the function.
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Now that phy_startup() can return an actual error code, check for that error
code and abort network initialization if the PHY fails.
Signed-off-by: Timur Tabi ti...@freescale.com
Acked-by: Nobuhiro Iwamamatsu nobuhiro.iwamatsu...@renesas.com (sh_eth part)
Acked-by: Stephan Linz l...@li-pro.net
The BR_PHYS_ADDR(x) macro was missing parentheses around x in the macro
definition, so callers had to supply their own parenthesis.
Signed-off-by: Timur Tabi ti...@freescale.com
---
arch/powerpc/include/asm/fsl_lbc.h |6 +++---
include/configs/MPC8536DS.h|9 -
include
Now that phy_startup() can return an actual error code, check for that error
code and abort network initialization if the PHY fails.
Signed-off-by: Timur Tabi ti...@freescale.com
---
drivers/net/fec_mxc.c |7 ++-
drivers/net/fm/eth.c |9 -
drivers/net
Wolfgang Denk wrote:
Blank line after variable declarations, please.
Oops. I'll wait to see if there are any other comments before I respin.
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phy_startup() calls the PHY driver's startup function, but it ignores the
return code from that function, and so it never returns any failures.
Signed-off-by: Timur Tabi ti...@freescale.com
---
drivers/net/phy/phy.c |5 -
1 files changed, 4 insertions(+), 1 deletions(-)
diff --git
Now that phy_startup() can return an actual error code, check for that error
code and abort network initialization if the PHY fails.
Signed-off-by: Timur Tabi ti...@freescale.com
---
drivers/net/fec_mxc.c |7 ++-
drivers/net/fm/eth.c |9 -
drivers/net
The misspelling of semiconductor causes some internal copyright analysis
tools to complain.
Signed-off-by: Timur Tabi ti...@freescale.com
---
arch/powerpc/cpu/mpc83xx/serdes.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/cpu/mpc83xx/serdes.c
b/arch
Hmmm... that's not a bad idea. I'll think about it.
but the ugliness comes from the hardware design, so we have no reasoin
to camouflage it. Let people see what is going on under the hood - if
this is done in a clean way, you don't have to be ashamed.
LOL.
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[b04825@efes u-boot.0]$
However, I just tried the two SDK patches
that add it, and they apply cleanly, so that's an easy fix.
Which patches are those?
powerpc/85xx: add SPI and SD builds for P1022DS
powerpc/p1022ds: Add support for NAND and NAND boot
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From: Matthew McClintock m...@freescale.com
Add TLB mappings, board target options, and configuration items
need for SPI/SD boot.
Since P1022DS RevB board, the NOR flash have been changed to 16 bit/28bit
address flash, therefore, when SDHC/ESPI booting and access to eLBC,
the PMUXCR[0~1] must be
From: Matthew McClintock m...@freescale.com
Add defines needed to access NAND, remove second flash bank that is
actually connected to NAND.
Add nand booting support for P1022DS with hardcoded DDR config
Signed-off-by: Matthew McClintock m...@freescale.com
Signed-off-by: Jerry Huang
p1022ds boot. This
will likely require reviving the three-stage boot discussion (TPL).
I just posted those two patches for upstream. I don't want the TPL work
to hold up these patches.
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on something else.
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don't know how
to make this work.
Well, *I* don't know how to do that.
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before switching to indirect mode.
Signed-off-by: Timur Tabi ti...@freescale.com
---
board/freescale/p1022ds/diu.c | 82 +
1 files changed, 74 insertions(+), 8 deletions(-)
diff --git a/board/freescale/p1022ds/diu.c b/board/freescale/p1022ds/diu.c
index
to %s...\n, env_name_spec);
return board_saveenv() ? 1 : 0;
}
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the wrong place for this.
If you have a better idea, then I'm all ears. I could implement my own
version of saveenv(), but the current design of U-boot does not allow me
to have two functions called saveenv().
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.
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Mike Frysinger wrote:
On Friday 04 May 2012 18:21:31 Timur Tabi wrote:
Introduce board_start_saveenv() and board_finish_saveenv(), two weak
functions that are called before and after saving the environment. This
allows for board-specific functions that prepare the board for saving
the NAND device */
chip-select_chip(mtd, -1);
}
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Dirk Eibach wrote:
Signed-off-by: Dirk Eibach eib...@gdsys.de
Cc: Timur Tabi ti...@freescale.com
---
Can you give me some instructions on how to test this? I'm working on
adding NAND boot support to the P1022, so I need to make sure I don't
conflict with your patch.
Changes in v2:
- add Cc
-by: Timur Tabi ti...@freescale.com
---
include/configs/P2020DS.h | 22 +-
1 files changed, 1 insertions(+), 21 deletions(-)
diff --git a/include/configs/P2020DS.h b/include/configs/P2020DS.h
index f0eb029..183d70a 100644
--- a/include/configs/P2020DS.h
+++ b/include/configs
fdt_set_phy_handle() makes several FDT calls that could fail, so it should
not be hiding these errors.
Signed-off-by: Timur Tabi ti...@freescale.com
---
board/freescale/common/fman.c | 36 +++-
board/freescale/common/fman.h |2 +-
2 files changed, 20
Remove some unused default environment variables (memctl_intlv_ctl,
perf_mode, diuregs, dium, and diuerr), update 'tftpflash' variable,
and add videobootargs as a Linux command line variable (so that we can
easily pass video= to the kernel).
Signed-off-by: Timur Tabi ti...@freescale.com
is normally unavailable (e.g. blocked via a mux).
Signed-off-by: Timur Tabi ti...@freescale.com
---
common/cmd_nvedit.c | 24 +++-
1 files changed, 23 insertions(+), 1 deletions(-)
diff --git a/common/cmd_nvedit.c b/common/cmd_nvedit.c
index e1ccdd8..9637682 100644
--- a/common
value to
a pointer anyway.
Signed-off-by: Timur Tabi ti...@freescale.com
---
arch/powerpc/include/asm/io.h |2 +-
include/addr_map.h|2 +-
lib/addr_map.c| 19 +++
3 files changed, 13 insertions(+), 10 deletions(-)
diff --git a/arch/powerpc/include
the mux for each NOR flash
transaction (which is what the current code does), and it also allows
us to support any localbus device, not just NOR flash.
Signed-off-by: Timur Tabi ti...@freescale.com
---
board/freescale/p1022ds/diu.c | 173 +++--
include/configs
, so you need to enable support for the ATI driver to see what is
and is not actually used. Just because it's not enabled currently in any
board, that doesn't mean that the code is useless.
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Marek Vasut wrote:
Agreed, but I expected there was some dead code and that was the point I was
trying to express ;-)
Well, until you do a thorough analysis, you really have no idea if there
is any dead code at all.
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to remove it from the P1022DS board. I think the only
reason it is enabled because of some misunderstanding of the BSP
requirement, and no one ever noticed.
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The CCSR relocation code in start.S writes to MAS7 on all e500 parts, but
that register does not exist on e500v1.
Signed-off-by: Timur Tabi ti...@freescale.com
---
arch/powerpc/cpu/mpc85xx/start.S |8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/cpu
/* Enable MAS7 */
#endif
So I don't think we can get rid of it, otherwise I suspect an e500v1
operating system will not work on an e500v2 part.
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since then -- Timur, could you look at this?
On e500v1 parts, CONFIG_SYS_CCSRBAR_PHYS_HIGH will always be 0, so it will
only write 0 to MAS7. Is that still considered a bad thing? The tlbwe
will ignore MAS7.
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1 sectors
This problem probably surfaced from some other change that significantly
increased the normal memory usage, thereby not leaving enough room for
the saveenv command.
Signed-off-by: Timur Tabi ti...@freescale.com
---
include/configs/MPC832XEMDS.h |2 +-
1 files changed, 1 insertions
which
size is being used. Not only that, but each board includes code that displays
the message, so there is duplication.
The 'bdinfo' command has been updated to display this information, so
we don't need to display it at boot time. The board-specific code is
deleted.
Signed-off-by: Timur Tabi ti
Some Freescale SOCs support 32-bit and 36-bit physical addressing, and
U-Boot must be built to enable one or the other. Add this information
to the bdinfo command.
Signed-off-by: Timur Tabi ti...@freescale.com
---
This patch set replaces the following patches:
http://patchwork.ozlabs.org/patch
is not writable until after relocation, and DDR initialization
requires I2C.
A board that has SPD on two different I2C buses could not be supported by
U-Boot today.
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Simon Glass wrote:
I agree completely, it was one of the things I was going to ask for.
We should add a new parameter to calls instead IMO.
I would be in favor of a patch that replaces all of the I2C calls. It
would be a massive patch, but it solve a lot of problems in one shot.
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Simon Glass wrote:
I agree. Do you know of such a patch? :-)
No, but it wouldn't be heard to create -- mostly a global
search-and-replace. I wouldn't even attempt it without getting
pre-approved by Wolfgang first, though.
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wrote:
The reason I ask is that you're missing some of my patches.
http://patchwork.ozlabs.org/project/uboot/list/?submitter=timur
Ok, technically you're only missing ONE of my patches.
http://patchwork.ozlabs.org/patch/118367/
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to 0xEFF4, which is the flash
sector adjacent to the environment.
Signed-off-by: Timur Tabi ti...@freescale.com
---
include/configs/P1023RDS.h |2 +-
include/configs/P2041RDB.h |2 +-
include/configs/corenet_ds.h |2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git
to upload the QE ucode
*before* the environment variables are available?
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Timur Tabi wrote:
Well, I tried that a while back and it didn't work, but I can't remember
why. That was before I implemented a unified approach to Fman ucode
identification, so maybe it will work better now.
Ok, I remember now.
The problem was that using the environment variable was messy
address.
No. The warning just says that microcode is invalid, not that that it's at the
wrong address.
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to 0xEFF4, which is the flash
sector adjacent to the environment. To support older boards, we use macro
CONFIG_SYS_QE_FMAN_FW_ADDR_OLD to look for the microcode in the old location
if it cannot be found in the new one.
Signed-off-by: Timur Tabi ti...@freescale.com
---
include/configs/P1023RDS.h |4
is not a firmware
Fman2: Uploading microcode version 101.8.0
Signed-off-by: Timur Tabi ti...@freescale.com
---
drivers/net/fm/fm.c |7 +++
1 files changed, 7 insertions(+), 0 deletions(-)
diff --git a/drivers/net/fm/fm.c b/drivers/net/fm/fm.c
index 0b8c33f..f148608 100644
--- a/drivers/net/fm/fm.c
+++ b
Kumar Gala wrote:
Can your respin against current upstream HEAD. For some reason this doesn't
apply cleanly there.
This patch broke it:
drivers/net/fm/fm.c: Fix GCC 4.6 build warning
I'll post a v2 in just a few minutes.
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by looking at a variable how it's supposed
to be used.
In the future, the code which uploads QE firmware and Fman firmware will
be merged.
Signed-off-by: Timur Tabi ti...@freescale.com
---
README | 38 +++
arch/powerpc/cpu/mpc85xx
for the
P1010 and P1014.
Signed-off-by: Timur Tabi ti...@freescale.com
---
arch/powerpc/include/asm/config_mpc85xx.h |6 ++
include/configs/P1022DS.h |1 -
include/configs/P2041RDB.h|5 ++---
include/configs/P3041DS.h |1 -
include
On the P1022/P1013, the work-around for erratum SATA_A001 was implemented
only if U-Boot initializes SATA, but SATA is not initialized by default. So
move the work-around to the CPU initialization function, so that it's always
executed on the SOCs that need it.
Signed-off-by: Timur Tabi ti
want that.
Since the lbc is a separate node, it's possible for the 'reg' property to
be wrong. This happened with the original version of p1022ds.dts, which
used a 32-bit value in the 'reg' address, instead of a 36-bit address.
Signed-off-by: Timur Tabi ti...@freescale.com
---
arch/powerpc/cpu
based on the u-boot ccsrbar,
why can't u-boot update the device tree?
Because we can't just relocate the devices that we know about and ignore the
rest. If CCSR is at the wrong address, then maybe the PCI memory ranges are
wrong, too? Who's to say what else is wrong?
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, SPI booting, etc). I also posted a patchset last week that
fixes a few problems with
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Ira W. Snyder wrote:
On Thu, Nov 10, 2011 at 11:12:41AM -0600, Timur Tabi wrote:
Ira W. Snyder wrote:
Hello Timur, Kumar, U-Boot List,
I'm working on porting U-Boot to the Freescale P2020 COM-Express board.
See the ML post from 2011-09-27 titled [PATCH 0/2] mpc85xx: support for
Freescale
u-boot image.
Ira says that early boot loader sets of DDR, so I presume it's running from
that, not SRAM.
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Ira W. Snyder wrote:
I boot using the on-chip ROM, loading U-Boot from SD card to DDR.
The on-chip creates a 4GB TLB, which breaks the CCSR code. My five-patch
patchset fixes this.
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by looking at a variable how it's supposed
to be used.
In the future, the code which uploads QE firmware and Fman firmware will
be merged.
Signed-off-by: Timur Tabi ti...@freescale.com
---
README | 38 +++
arch/powerpc/cpu/mpc85xx
Kim Phillips wrote:
4. no need to clear BATs before writing them either.
FYI, take a look at Becky's BAT patch from a month ago:
http://patchwork.ozlabs.org/patch/117523/
The patch is for 86xx, so I have no idea if it's relevant to this discussion.
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Some of the EEPROM Word Offset macros, and a few others, are defined
twice in e1000.h.
Signed-off-by: Timur Tabi ti...@freescale.com
---
drivers/net/e1000.h | 11 ---
1 files changed, 0 insertions(+), 11 deletions(-)
diff --git a/drivers/net/e1000.h b/drivers/net/e1000.h
index
was always been 'tsize'.
Signed-off-by: Timur Tabi ti...@freescale.com
---
arch/powerpc/include/asm/mmu.h | 10 +-
1 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/powerpc/include/asm/mmu.h b/arch/powerpc/include/asm/mmu.h
index ef5076b..209103e 100644
--- a/arch/powerpc
Calls to tlbwe and tlbsx should be preceded with an isync/msync pair.
Signed-off-by: Timur Tabi ti...@freescale.com
---
arch/powerpc/cpu/mpc85xx/start.S |4
1 files changed, 4 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S
On some Freescale systems (e.g. those booted from the on-chip ROM), the
TLB that covers the boot page can also cover CCSR, which breaks the CCSR
relocation code. To fix this, we resize the boot page TLB so that it only
covers the 4KB boot page.
Signed-off-by: Timur Tabi ti...@freescale.com
.
Signed-off-by: Timur Tabi ti...@freescale.com
---
arch/powerpc/cpu/mpc85xx/start.S | 27 +++
1 files changed, 27 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S
index ccb331a..6de8765 100644
--- a/arch
Signed-off-by: Timur Tabi ti...@freescale.com
---
arch/powerpc/cpu/mpc85xx/start.S |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S
index 528abc9..b5bf1fa 100644
--- a/arch/powerpc/cpu/mpc85xx/start.S
Kumar Gala wrote:
Need Wolfgang's Ack on that.
Why? It just fixes a bug in our board code.
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it anywhere, though.
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The EC1_EXT, EC2_EXT, and EC3 bits in the RCW don't officially exist on the
P3060 and should always be set to zero.
Signed-off-by: Timur Tabi ti...@freescale.com
---
arch/powerpc/cpu/mpc85xx/p3060_serdes.c | 20
arch/powerpc/include/asm/immap_85xx.h | 10
for PowerPC.
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-by: Timur Tabi ti...@freescale.com
---
board/freescale/corenet_ds/corenet_ds.c |4
board/freescale/mpc8536ds/mpc8536ds.c |7 +--
board/freescale/mpc8572ds/mpc8572ds.c |6 +-
board/freescale/p1010rdb/p1010rdb.c |6 +-
board/freescale/p1022ds/p1022ds.c
Before the Teranetics TN2020 PHY can be used, the SERDES lanes need to be
aligned, so wait for lane alignment before completing the startup sequence.
Note that this process can take up to three seconds.
Signed-off-by: Timur Tabi ti...@freescale.com
---
drivers/net/phy/teranetics.c | 33
The work-around for P4080 erratum SERDES9 says that the SERDES receiver lanes
should be reset after the XAUI starts tranmitting alignment signals.
Signed-off-by: Timur Tabi ti...@freescale.com
---
arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c | 10 --
board/freescale/corenet_ds/eth_p4080.c
a hard-coded number.
Are you suggesting that I create a header file just to contain this line:
extern struct phy_driver tn2020_driver;
because that seems silly.
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stricter than for Linux? It appears that you are requiring exact
conformance to checkpatch, even when it complains about something that isn't
really that bad.
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From: Andy Fleming aflem...@freescale.com
The Teranetics PHY does not properly report the link state
for fiber connections. The new PHY code actually checked the link,
and so the FM driver would refuse to talk over a linkless PHY.
But the link may actually be up, so now we always report it as up
The work-around for P4080 erratum SERDES9 says that the SERDES receiver lanes
should be reset after the XAUI starts tranmitting alignment signals.
Signed-off-by: Timur Tabi ti...@freescale.com
---
arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c | 10 --
board/freescale/corenet_ds/eth_p4080.c
Before the Teranetics TN2020 PHY can be used, the SERDES lanes need to be
aligned, so wait for lane alignment before completing the startup sequence.
Note that this process can take up to three seconds.
Signed-off-by: Timur Tabi ti...@freescale.com
---
drivers/net/phy/teranetics.c | 32
The print_str() helper function for cmd_bdinfo can print any string, but it
is only used to print MHz values. Replace it with print_mhz() that takes
a number and converts it to a string internally.
Signed-off-by: Timur Tabi ti...@freescale.com
---
This patch applies on top of powerpc/85xx
, it is used by dtsec_configure_serdes() to configure the TBI PHY
registers.
We also need to define the PHY registers in struct fm_mdio.
Signed-off-by: Timur Tabi ti...@freescale.com
---
Note: I'm not sure of my change to struct fm_mdio. It works, but it doesn't
smell right.
arch/powerpc
, since
it has to check for two properties instead of one in each node that it
searches.
Signed-off-by: Timur Tabi ti...@freescale.com
---
common/fdt_support.c |7 ++-
1 files changed, 2 insertions(+), 5 deletions(-)
diff --git a/common/fdt_support.c b/common/fdt_support.c
index 698abf7
. Instead, change it to use
fdt_create_phandle().
Signed-off-by: Timur Tabi ti...@freescale.com
---
arch/powerpc/cpu/mpc85xx/fdt.c |5 ++---
1 files changed, 2 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c
index d20c94c..9d2d769
fdt_create_phandle() was ignoring errors from fdt_set_phandle(). If an
error occurs, print an error message and return 0, which is an invalid
phandle. We also need to change the return type for fdt_create_phandle()
to indicate that it cannot return an error code.
Signed-off-by: Timur Tabi ti
for such a powerful feature. How about some examples and
a detailed description of each command?
--
Timur Tabi
Linux kernel developer at Freescale
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could it be too long? Is there not enough room on the git server to store a
text file? This file could be 200KB is size, and that would be okay.
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Linux kernel developer at Freescale
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Scott Wood wrote:
There's no way it can be 3000, 6600, etc. based on the board's
crystal?
There is earlier code that sets pci1_speed to if the speed is unknown.
So the actual value of pci1_speed is limited to those two numbers.
--
Timur Tabi
Linux kernel developer
difficult for
people to review the patch, but I'm sure that Chenhui already knows that.
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Linux kernel developer at Freescale
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-by: Timur Tabi ti...@freescale.com
---
board/freescale/corenet_ds/corenet_ds.c |4
board/freescale/mpc8536ds/mpc8536ds.c |7 +--
board/freescale/mpc8572ds/mpc8572ds.c |6 +-
board/freescale/p1010rdb/p1010rdb.c |6 +-
board/freescale/p1022ds/p1022ds.c
The macro CONFIG_ENABLE_36BIT_PHYS is used to indicate that the given SOC is
capable of 36-bit physical addresses, even if such large addresses are not
used. On two boards, this macro was enabled only when building a 36-bit
image.
Signed-off-by: Timur Tabi ti...@freescale.com
---
include
lines into one:
CPU0: P1022E, Version: 1.0, (0x80ee0010)
Core: E500, Version: 5.0, (0x80211050)
or these two lines:
L1:D-cache 32 kB enabled
I-cache 32 kB enabled
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Timur Tabi
Linux kernel developer at Freescale
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