Please forget the last phrase...
On Mon, Oct 26, 2009 at 5:01 PM, Werner Nedel wmne...@gmail.com wrote:
Sorry for this big mistake and wasting your time :-(
There's a bit between rtt and ocd, that don't match with definition in
jedec ddr2 sdram specification.
On Sat, Oct 24, 2009 at 12:38
*/
| ((0x1) 2) /* rtt field is split */
);
esdmode = (0
| (0x40) /* rtt field is split */
| (0x4) /* rtt field is split */
);
esdmode = (0x44);
- k
On Oct 22, 2009, at 9:53 AM, Werner Nedel wrote
,
Werner Nedel.
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Hi,
sorry about that. I'm working on a MPC8548 platform and using the mpc8xxx
common code for DDR configuration.
On Thu, Oct 22, 2009 at 11:36 AM, Kumar Gala ga...@kernel.crashing.orgwrote:
On Oct 22, 2009, at 6:48 AM, Werner Nedel wrote:
Hi,
I was looking the ctrl_regs.c file
Sorry again,
and with DDR2.
On Thu, Oct 22, 2009 at 11:42 AM, Werner Nedel wmne...@gmail.com wrote:
Hi,
sorry about that. I'm working on a MPC8548 platform and using the mpc8xxx
common code for DDR configuration.
On Thu, Oct 22, 2009 at 11:36 AM, Kumar Gala ga...@kernel.crashing.orgwrote
Hi,
I'm having a big problem with my board reset that it's very similar to
MPC8548CDS. I've been using for a long time a reset just in MPC8548 core,
using DBCR0 register. But after many resets, my u-boot crash when try to
relocate code to ram, and I can't debug it with BDI.
I saw the MPC8548
The time that the sequencer power source stays the HRESET down is
configurable, as the time waiting to rise up.
On Tue, Aug 25, 2009 at 11:14 AM, Werner Nedel wmne...@gmail.com wrote:
Hi,
I'm having a big problem with my board reset that it's very similar to
MPC8548CDS. I've been using
Maybe I'm confusing DDR controller with SPD eeprom. My board have 2 SPDs in
0x51 and 0x53, one for each DIMM. I tought that I should set 2 DDR
controllers to fsl_ddr_get_spd() takes the information of them in
cpu/mpc8xxx/ddr/main.c.
for (i = 0; i CONFIG_NUM_DDR_CONTROLLERS; i++) {
Thanks for the advice. I'll try to set the correct configurations and adjust
my ddr.c.
On Fri, May 15, 2009 at 10:56 AM, Werner Nedel wmne...@gmail.com wrote:
Maybe I'm confusing DDR controller with SPD eeprom. My board have 2 SPDs in
0x51 and 0x53, one for each DIMM. I tought that I should
: 2 GB
The tlb settings looks fine (debbug in setup_ddr_tlbs()):
ram_tlb_address: 0x0, ram_tlb_address: 0x0, ram_tlb_index: 0x8, tlb_size:
0xa
ram_tlb_address: 0x4000, ram_tlb_address: 0x4000, ram_tlb_index:
0x9, tlb_size: 0xa
Am I missing some configuration?
Thanks in advance,
Werner
Interesting. I've tried to use your patch but still hanging board_init_f.
Even putting BOOKE_PAGESZ_256M in set_tlb the problem occur.
On Thu, May 14, 2009 at 2:49 PM, Fredrik Arnerup
fredrik.arne...@edgeware.tv wrote:
The tlb settings looks fine (debbug in setup_ddr_tlbs()):
Right, I'm being sure to erase it each time before I try ubi part,
just to limit the number of variables. I'm trying to do:
nand erase 50 (0x50 is the start of my UBI partition)
mtdparts default (assigns 0x50 and up to root partition)
ubi part root
Should you have to pass the
(fff8 to works fine), but it can be a problem in my
flash driver.
Thanks for your help,
Werner Nedel.
On Thu, Apr 16, 2009 at 8:12 PM, Kumar Gala ga...@kernel.crashing.orgwrote:
On Apr 9, 2009, at 1:03 PM, Werner Nedel wrote:
I'm trying to update my u-boot version (1.2
:03 PM, Werner Nedel wmne...@gmail.com wrote:
Hi,
I'm trying to update my u-boot version (1.2) to the last one (2009.03). My
board is very similar to MPC8548CDS. Everything was working fine till I
tried to use the reset command. It hangs the processor in cpu_init_early_f,
when it realocates
:
.bootpg ADDR(.text) + 0x7f000 :
{
cpu/mpc85xx/start.o(.bootpg)
} :text = 0x
.resetvec 0xfff8 + 0x7fffc :
.resetvec ADDR(.text) + 0x7fffc :
{
*(.resetvec)
} :text = 0x
. = 0xfff8 + 0x8;
. = ADDR(.text) + 0x8;
Thanks in advance,
Werner Nedel
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