The power gating feature of pl2 should be enabled as early as possible,
it would be better to put it in SPL stage.
Signed-off-by: Zong Li
---
arch/riscv/lib/sifive_cache.c | 21 +
1 file changed, 21 insertions(+)
diff --git a/arch/riscv/lib/sifive_cache.c b/arch/riscv/lib
SiFive private L2 cache is per core cache, add this driver to control
its features by a MMIO register. In this series, we try to enable the
power gating feature of pL2 cache in SPL stage
Zong Li (2):
cache: add sifive private L2 cache driver
riscv: cache: support cache enable in SPL stage
This driver is currently responsible for enabling the clock gating
feature of SiFive pre core's private L2 cache.
Signed-off-by: Zong Li
---
drivers/cache/Kconfig| 7 +
drivers/cache/Makefile | 1 +
drivers/cache/cache-sifive-pl2.c | 44
On Mon, Feb 6, 2023 at 3:58 PM Leo Liang wrote:
>
> Hi Simon,
>
> On Thu, Feb 02, 2023 at 10:25:36AM -0700, Simon Glass wrote:
> > Hi,
> >
> > On Thu, 2 Feb 2023 at 10:18, Simon Glass wrote:
> > >
> > > Hi Rick & Leo,
> > >
> > > I see docs for one board at [1] but I'm not sure what to do with
On Wed, Feb 8, 2023 at 4:07 PM Rick Chen wrote:
>
> Hi Zong,
>
> > From: Leo Yu-Chi Liang(梁育齊)
> > Sent: Monday, February 06, 2023 3:58 PM
> > To: Simon Glass
> > Cc: U-Boot Mailing List ; Rick Jian-Zhi Chen(陳建志)
> > ; zong...@sifive.com; vincent.c...@sifive.com
> > Subject: Re: Docs for
On Mon, Nov 21, 2022 at 8:17 PM Zong Li wrote:
>
> On Mon, Nov 21, 2022 at 12:00 PM Sean Anderson wrote:
> >
> > On 11/16/22 02:08, Zong Li wrote:
> > > Use imply instead of select, then it can still be disabled by
> > > board-specific defconfig, or be set t
On Mon, Nov 21, 2022 at 12:00 PM Sean Anderson wrote:
>
> On 11/16/22 02:08, Zong Li wrote:
> > Use imply instead of select, then it can still be disabled by
> > board-specific defconfig, or be set to n manually.
> >
> > Signed-off-by: Zong Li
> > ---
&g
Use imply instead of select, then it can still be disabled by
board-specific defconfig, or be set to n manually.
Signed-off-by: Zong Li
---
arch/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/Kconfig b/arch/Kconfig
index ae39716697..102956d24c 100644
--- a/arch
On Wed, Sep 29, 2021 at 6:17 PM Ilias Apalodimas
wrote:
>
> On Wed, Sep 29, 2021 at 12:02:16PM +0300, Ilias Apalodimas wrote:
> > Hi Zong,
> >
> > [...]
> >
> > > > diff --git a/board/sifive/unleashed/unleashed.c
> > > > b/board/sifive/unleashed/unleashed.c
> > > > index
On Mon, Sep 27, 2021 at 2:48 PM Ilias Apalodimas
wrote:
>
> At some point back in 2018 prior_stage_fdt_address and OF_PRIOR_STAGE got
> introduced, in order to support a DTB handed over by an earlier stage boo
> loader. However we have another option in the Kconfig (OF_BOARD) which has
>
Invokes the common cache_init function to initialize ccache.
Signed-off-by: Zong Li
Reviewed-by: Sean Anderson
---
arch/riscv/cpu/fu540/Kconfig | 2 +
arch/riscv/cpu/fu540/Makefile | 1 -
arch/riscv/cpu/fu540/cache.c | 55 ---
arch
We usually use a space in function declaration, rather than a tab.
Signed-off-by: Zong Li
Reviewed-by: Sean Anderson
---
arch/riscv/include/asm/cache.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/riscv/include/asm/cache.h b/arch/riscv/include/asm/cache.h
index
-by: Zong Li
---
arch/riscv/Kconfig| 5 +
arch/riscv/lib/Makefile | 1 +
arch/riscv/lib/sifive_cache.c | 27 +++
3 files changed, 33 insertions(+)
create mode 100644 arch/riscv/lib/sifive_cache.c
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
The enable_caches is a generic hook for architecture-implemented, we
leverage this function to enable caches for RISC-V
Signed-off-by: Zong Li
---
arch/riscv/lib/cache.c | 4
common/board_r.c | 4 ++--
2 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/arch/riscv/lib
-off-by: Zong Li
Reviewed-by: Sean Anderson
Reviewed-by: Rick Chen
---
drivers/cache/Kconfig | 7 +++
drivers/cache/Makefile | 1 +
drivers/cache/cache-sifive-ccache.c | 75 +
3 files changed, 83 insertions(+)
create mode 100644 drivers
to v2021.10-rc3
Changed in v3:
- Combine some patches
- Drop the subdirectories of vendor in lib/
- Rebase codebase
Changed in v2:
- Refine the ccache driver by Sean's suggestions
- Introduce a common interface for cache initialization
Zong Li (5):
cache: add sifive composable cache driver
On Wed, Sep 1, 2021 at 10:06 AM Rick Chen wrote:
>
> > From: Zong Li
> > Sent: Tuesday, August 31, 2021 5:21 PM
> > To: Rick Jian-Zhi Chen(陳建志) ; Leo Yu-Chi Liang(梁育齊)
> > ; bmeng...@gmail.com; sean...@gmail.com;
> > green@sifive.com; paul.walms...@sifi
On Tue, Aug 31, 2021 at 12:48 PM Sean Anderson wrote:
>
> On 8/17/21 5:08 AM, Zong Li wrote:
> > Add an interface for cache initialization. Each platform can overwrite
> > this weak function by their own implementation, such as sifive_cache in
> > this patch.
> >
&
We usually use a space in function declaration, rather than a tab.
Signed-off-by: Zong Li
Reviewed-by: Sean Anderson
---
arch/riscv/include/asm/cache.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/riscv/include/asm/cache.h b/arch/riscv/include/asm/cache.h
index
Invokes the common cache_init function to initialize ccache.
Signed-off-by: Zong Li
Reviewed-by: Sean Anderson
---
arch/riscv/cpu/fu540/Kconfig | 2 +
arch/riscv/cpu/fu540/Makefile | 1 -
arch/riscv/cpu/fu540/cache.c | 55 ---
arch
-by: Zong Li
---
arch/riscv/Kconfig| 5 +
arch/riscv/lib/Makefile | 1 +
arch/riscv/lib/sifive_cache.c | 27 +++
common/board_r.c | 4 ++--
4 files changed, 35 insertions(+), 2 deletions(-)
create mode 100644 arch/riscv/lib/sifive_cache.c
-off-by: Zong Li
Reviewed-by: Sean Anderson
---
drivers/cache/Kconfig | 7 +++
drivers/cache/Makefile | 1 +
drivers/cache/cache-sifive-ccache.c | 75 +
3 files changed, 83 insertions(+)
create mode 100644 drivers/cache/cache-sifive
- Drop the subdirectories of vendor in lib/
- Rebase codebase
Changed in v2:
- Refine the ccache driver by Sean's suggestions
- Introduce a common interface for cache initialization
Zong Li (4):
cache: add sifive composable cache driver
riscv: lib: implement enable_caches for sifive cache
On Tue, Aug 17, 2021 at 5:08 PM Zong Li wrote:
>
> This patch set contains the SiFive composable cache support, and
> indroduce an interface to do cache initialization, each platform can
> overwrite it by their own implementation.
>
> Changed in v3:
> - Combine s
Invokes the common cache_init function to initialize ccache.
Signed-off-by: Zong Li
---
arch/riscv/cpu/fu540/Kconfig | 2 +
arch/riscv/cpu/fu540/Makefile | 1 -
arch/riscv/cpu/fu540/cache.c | 55 ---
arch/riscv/cpu/fu740/Kconfig
We usually use a space in function declaration, rather than a tab.
Signed-off-by: Zong Li
Reviewed-by: Sean Anderson
---
arch/riscv/include/asm/cache.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/riscv/include/asm/cache.h b/arch/riscv/include/asm/cache.h
index
.
Signed-off-by: Zong Li
---
arch/riscv/Kconfig | 5 +
arch/riscv/include/asm/cache.h | 1 +
arch/riscv/lib/Makefile| 1 +
arch/riscv/lib/cache.c | 5 +
arch/riscv/lib/sifive_cache.c | 27 +++
5 files changed, 39 insertions
-off-by: Zong Li
Reviewed-by: Sean Anderson
---
drivers/cache/Kconfig | 7 +++
drivers/cache/Makefile | 1 +
drivers/cache/cache-sifive-ccache.c | 75 +
3 files changed, 83 insertions(+)
create mode 100644 drivers/cache/cache-sifive
:
- Refine the ccache driver by Sean's suggestions
- Introduce a common interface for cache initialization
Zong Li (4):
cache: add sifive composable cache driver
riscv: lib: introduce a cache_init interface
board: sifive: use ccache driver instead of helper function
riscv: lib: modify
On Fri, Aug 13, 2021 at 4:20 AM Sean Anderson wrote:
>
> On 8/10/21 2:57 AM, Zong Li wrote:
> > On Tue, Aug 10, 2021 at 12:47 PM Sean Anderson wrote:
> >>
> >> On 8/3/21 12:44 AM, Zong Li wrote:
> >>> Add an interface for cache initialization. Each platf
On Fri, Aug 13, 2021 at 4:22 AM Sean Anderson wrote:
>
> On 8/10/21 3:04 AM, Zong Li wrote:
> > On Tue, Aug 10, 2021 at 12:55 PM Sean Anderson wrote:
> >>
> >>> Re: [PATCH v2 5/6] riscv: lib: move platform-related libraries to sperate
> >>> folde
On Tue, Aug 10, 2021 at 12:55 PM Sean Anderson wrote:
>
> > Re: [PATCH v2 5/6] riscv: lib: move platform-related libraries to sperate
> > folder
>
> nit: separate
>
Thanks for catching it. Fix it in the next version.
> On 8/3/21 12:44 AM, Zong Li wrote:
&
On Tue, Aug 10, 2021 at 12:47 PM Sean Anderson wrote:
>
> On 8/3/21 12:44 AM, Zong Li wrote:
> > Add an interface for cache initialization. Each platform can overwrite
> > this weak function by their own implementation, such as sifive_cache in
> > this patch.
>
>
On Tue, Aug 10, 2021 at 12:51 PM Sean Anderson wrote:
>
> On 8/3/21 12:44 AM, Zong Li wrote:
> > Invokes the generic cache_enable interface to execute the relative
> > implementation in SiFive ccache driver.
> >
> > Signed-off-by: Zong Li
> > --
We usually use a space in function declaration, rather than a tab.
Signed-off-by: Zong Li
---
arch/riscv/include/asm/cache.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/riscv/include/asm/cache.h b/arch/riscv/include/asm/cache.h
index 6ebb2b4329..b700ff5021 100644
Put the platform-related implementation into their own folder
respectively. Just leave the common library in the top of lib
folder.
Signed-off-by: Zong Li
---
arch/riscv/Kconfig | 7 +++
arch/riscv/lib/Makefile | 9 -
arch/riscv/lib
We already extracted the duplicated implementation to common code, so
change to use that and drop the original implementation.
Signed-off-by: Zong Li
---
arch/riscv/cpu/fu540/Kconfig | 1 +
arch/riscv/cpu/fu540/Makefile | 1 -
arch/riscv/cpu/fu540/cache.c
Add an interface for cache initialization. Each platform can overwrite
this weak function by their own implementation, such as sifive_cache in
this patch.
Signed-off-by: Zong Li
---
arch/riscv/Kconfig | 5 +
arch/riscv/include/asm/cache.h | 1 +
arch/riscv/lib/Makefile
Invokes the generic cache_enable interface to execute the relative
implementation in SiFive ccache driver.
Signed-off-by: Zong Li
---
arch/riscv/cpu/fu540/Kconfig | 1 +
arch/riscv/cpu/fu540/cache.c | 54 ++-
arch/riscv/cpu/fu740/Kconfig
-off-by: Zong Li
---
drivers/cache/Kconfig | 7 +++
drivers/cache/Makefile | 1 +
drivers/cache/cache-sifive-ccache.c | 75 +
3 files changed, 83 insertions(+)
create mode 100644 drivers/cache/cache-sifive-ccache.c
diff --git a/drivers
Zong Li (6):
cache: add sifive composable cache driver
board: sifive: use ccache driver instead of helper function
riscv: lib: introduce cache_init interface
riscv: sifive: use common cache_init instead of duplicated
implementation
riscv: lib: move platform-related libraries
Fixed the typo of date of copyright declaration.
Signed-off-by: Zong Li
---
arch/riscv/cpu/fu740/spl.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/riscv/cpu/fu740/spl.c b/arch/riscv/cpu/fu740/spl.c
index 55e30346ff..c6816e9ed4 100644
--- a/arch/riscv/cpu/fu740/spl.c
On Thu, Jul 29, 2021 at 8:26 PM Zong Li wrote:
>
> On Wed, Jul 28, 2021 at 11:18 PM Sean Anderson wrote:
> >
> > On 7/28/21 3:25 AM, Zong Li wrote:
> > > On Wed, Jul 28, 2021 at 12:29 PM Sean Anderson wrote:
> > >>
> > >> On 7/27/21
On Wed, Jul 28, 2021 at 11:18 PM Sean Anderson wrote:
>
> On 7/28/21 3:25 AM, Zong Li wrote:
> > On Wed, Jul 28, 2021 at 12:29 PM Sean Anderson wrote:
> >>
> >> On 7/27/21 4:54 AM, Zong Li wrote:
> >>> Invokes the generic cache_enable interface to
On Wed, Jul 28, 2021 at 12:23 PM Sean Anderson wrote:
>
> On 7/27/21 4:54 AM, Zong Li wrote:
> > This driver is currently responsible for enabling all ccache ways.
>
> Can you expand on this a little? Perhaps describe the hardware a little. For
> example,
> you could
On Wed, Jul 28, 2021 at 12:29 PM Sean Anderson wrote:
>
> On 7/27/21 4:54 AM, Zong Li wrote:
> > Invokes the generic cache_enable interface to execute the relative
> > implementation in SiFive ccache driver.
> >
> > Signed-off-by: Zong Li
> > --
.
Signed-off-by: Zong Li
---
board/sifive/unleashed/unleashed.c | 11 +++
board/sifive/unmatched/unmatched.c | 11 +++
2 files changed, 22 insertions(+)
diff --git a/board/sifive/unleashed/unleashed.c
b/board/sifive/unleashed/unleashed.c
index a4e78220cb..fa65fcade0 100644
As (3581811dc26f "riscv: sifive/fu540: Move SPL related functions to spl.c"),
we put the SPL stuff in spl.c, we don't need to compile unleashed.c and
unmatched.c in SPL build.
Signed-off-by: Zong Li
---
board/sifive/unleashed/Makefile | 4 ++--
board/sifive/unmatched/Makefile | 3 ++
Invokes the generic cache_enable interface to execute the relative
implementation in SiFive ccache driver.
Signed-off-by: Zong Li
---
arch/riscv/cpu/fu540/Kconfig | 1 +
arch/riscv/cpu/fu540/cache.c | 62 ---
arch/riscv/cpu/fu740/Kconfig
This driver is currently responsible for enabling all ccache ways.
Signed-off-by: Zong Li
---
drivers/cache/Kconfig | 7 +++
drivers/cache/Makefile | 1 +
drivers/cache/cache-sifive-ccache.c | 69 +
3 files changed, 77 insertions
On Wed, Jul 14, 2021 at 2:56 PM Leo Liang wrote:
>
> Hi Zong,
>
> On Fri, Jul 09, 2021 at 04:06:01PM +0800, Zong Li wrote:
> > This patch reverts the following commits:
> > - 4b4159d0f3 ("riscv: dts: add dts for unmatched rev1")
> > - ffe9a394d
hey might be useless.
Changed in v2:
- rebase codebase to the latest master branch
Signed-off-by: Zong Li
Suggested-by: David Abdurachmanov
Reviewed-by: Leo Yu-Chi Liang
---
arch/riscv/dts/Makefile |2 +-
.../fu740-hifive-unmatched-a00-ddr-rev1.dtsi | 1489 --
We wouldn't like to allow user to change the serial number, so remove
the command for changing serial number in EEPROM.
Signed-off-by: Zong Li
Suggested-by: David Abdurachmanov
---
.../unmatched/hifive-platform-i2c-eeprom.c| 23 +--
1 file changed, 1 insertion(+), 22
hey might be useless.
Signed-off-by: Zong Li
Suggested-by: David Abdurachmanov
---
arch/riscv/dts/Makefile |2 +-
.../fu740-hifive-unmatched-a00-ddr-rev1.dtsi | 1489 -
.../dts/hifive-unmatched-a00-rev1-u-boot.dtsi |7 -
arch/riscv/dts/hifive-un
The difference between unmatched rev3 and rev1 is DDR timing, the rev3
uses 1866 MT/s for 16GiB, and rev1 uses 2133 MT/s for 8GiB.
Signed-off-by: Zong Li
---
arch/riscv/dts/Makefile |2 +-
.../fu740-hifive-unmatched-a00-ddr-rev1.dtsi | 1489 +
.../dts
There are two revisions of unmatched board with different DDR timing,
we'd like to support multi-dtb mechanism in SPL, then it selects the
right DTB at runtime according to PCB revision in I2C EEPROM.
Signed-off-by: Zong Li
---
board/sifive/unmatched/spl.c | 28
There are different DDR parameter settings for different board
revisions. Add a new interface to get the PCB revision to determine
which DT should be selected at runtime.
Signed-off-by: Zong Li
---
arch/riscv/include/asm/arch-fu740/eeprom.h| 15 +
.../unmatched/hifive-platform-i2c
Enable SPL_I2C_SUPPORT for fu740, and add 'u-boot,dm-spl' property in
i2c node.
Signed-off-by: Zong Li
---
arch/riscv/cpu/fu740/Kconfig | 1 +
arch/riscv/dts/fu740-c000-u-boot.dtsi | 4
2 files changed, 5 insertions(+)
diff --git a/arch/riscv/cpu/fu740/Kconfig b/arch/riscv/cpu
Add initial support for the PCB description EEPROM for SiFive HiFive
Unmatched boards.
This implementation is refactored based on Paul Walmsley's porting and
adopt the suggestions from David Abdurachmanov.
Signed-off-by: Paul Walmsley
Signed-off-by: David Abdurachmanov
Signed-off-by: Zong Li
Enable the Opencores I2C controller on FU740
Signed-off-by: Zong Li
---
arch/riscv/cpu/fu740/Kconfig | 2 ++
board/sifive/unmatched/Kconfig | 1 +
2 files changed, 3 insertions(+)
diff --git a/arch/riscv/cpu/fu740/Kconfig b/arch/riscv/cpu/fu740/Kconfig
index 3a5f6e47f5..1dc052ba31 100644
EEPROM to initialize the right DDR timing.
The I2C EEPROM support is refactored based on Paul Welmsley's porting
and adopt many suggestions from David Abdurachmanov.
Zong Li (6):
board: sifive: unmatched: add initial support for a platform ID EEPROM
riscv: sifive: fu740: kconfig: Enable support
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