On Oct 30, 2013, at 9:55 PM, Jain Priyanka-B32167 wrote:
-Original Message-
From: sun york-R58495
Sent: Wednesday, October 30, 2013 10:14 PM
To: Jain Priyanka-B32167; u-boot@lists.denx.de
Cc: Aggrwal Poonam-B10812
Subject: Re: [PATCH] powerpc/t1040qds: Add DDR Raw Timing support
On Oct 24, 2013, at 6:54 PM, Haijun Zhang wrote:
T4240 eSDHC host capabilities reigster should have VS33 bit define.
hack the code to add the 3.3 voltage support
Shall we call it quirk rather than hack? Native English speakers, please chime
in.
York
On Sep 25, 2013, at 4:52 PM, Scott Wood wrote:
On Wed, 2013-09-25 at 16:30 -0700, York Sun wrote:
Dear Wolfgang,
I failed to find the guideline, here is my question. Pardon me if this
is a dump question as I am still new to ARM.
As David Feng post his patch set to add ARMv8 support, I
On Sep 25, 2013, at 10:23 PM, FengHua wrote:
Date: Wed, 25 Sep 2013 20:10:13 -0500
From: Scott Wood scottw...@freescale.com
Subject: Re: [U-Boot] When to create a SoC directory for ARM
To: sun york-R58495 r58...@freescale.com
Cc: Rini tr...@ti.com, Wood Scott-B07421 b07
-boot-boun...@lists.denx.de [mailto:u-boot-boun...@lists.denx.de]
On Behalf Of York Sun
Sent: Wednesday, September 11, 2013 1:56 AM
To: u-boot@lists.denx.de
Cc: sun york-R58495
Subject: [U-Boot] [PATCH] powerpc/mpc8xxx: Fix CamelCase for DDR code
Clean up CamelCase in DDR code to comply
york-R58495 ; Xie Shaohui-B21989 ; aflem...@freescale.com
Subject: P2041RDB fails to boot with master (and 2013.10-rc1)
Hi,
I was just looking at something else and found that my P2041RDB no
longer boots from the master branch of u-boot.git (it hangs after DDR
initialisation). I checked 2013.10
22:49
To: sun york-R58495
CC: u-boot ; Xie Shaohui-B21989 ; h...@denx.de
Subject: Re: P2041RDB fails to boot with master (and 2013.10-rc1)
git bisect points to the following commit
00f792e0df9ae942427e44595a0f4379582accee is the first bad commit
commit 00f792e0df9ae942427e44595a0f4379582accee
On Aug 21, 2013, at 7:51 PM, Marek Vasut wrote:
Dear York Sun,
On 05/20/2013 10:25 AM, Marek Vasut wrote:
Prefix HOSTCC and CC with CCACHE variable to allow easy use of ccache.
In case the user wants to use ccache, exporting CCACHE=ccache will do
the trick. It is of course possible to
On Aug 21, 2013, at 10:02 PM, Marek Vasut wrote:
Dear sun york-R58495,
On Aug 21, 2013, at 7:51 PM, Marek Vasut wrote:
Dear York Sun,
On 05/20/2013 10:25 AM, Marek Vasut wrote:
Prefix HOSTCC and CC with CCACHE variable to allow easy use of ccache.
In case the user wants to use ccache
On Aug 21, 2013, at 10:45 PM, sun york-R58495 wrote:
On Aug 21, 2013, at 10:02 PM, Marek Vasut wrote:
Dear sun york-R58495,
On Aug 21, 2013, at 7:51 PM, Marek Vasut wrote:
Dear York Sun,
On 05/20/2013 10:25 AM, Marek Vasut wrote:
Prefix HOSTCC and CC with CCACHE variable to allow
On Aug 14, 2013, at 7:25 PM, Zhang Ying-B40530 wrote:
York,
I had checked all the patch and I am sure there is only this patch
almost forgotten.
I don't know how to do. Need I send the patch again or other way?
Thanks.
No need to resend. I can mark it. Just want to be
On Apr 7, 2013, at 1:29 AM, Wolfgang Denk wrote:
Dear sun york-R58495,
In message
c707e9f4d8007146bf8dc1424b113ac70b3a4...@039-sn2mpn1-012.039d.mgd.msft.net
you wrote:
Can we not split this into:
dcache flush
icache invalidate
? This would make clear what's happening
On Apr 6, 2013, at 12:01 AM, Wolfgang Denk wrote:
Dear York Sun,
In message 515f5812.8030...@freescale.com you wrote:
adding new:
dcache flush= flush all
dcache flush addr size = flush range
I think this makes more sense. Comments?
It would if
On Jan 7, 2013, at 10:35 PM, Wolfgang Denk wrote:
Dear York Sun,
In message 1357323245-12455-1-git-send-email-york...@freescale.com you
wrote:
...
CONFIG_FSL_DDR_INTERACTIVE needs to be defined in header file. To enter the
debug mode by key press, press key 'd' shortly after reset, like
Tom,
It's like eeprom write but it writes to general devices, not specificly to
system eeprom. I would have to use i2c mw command a lot without this.
York
Original Message
From: Tom Rini
Sent: Mon, Sep 17, 2012 05:16 PM
To: sun york-R58495
CC: u-boot@lists.denx.de; u-boot
Timur,
That patch itself is OK. But the comment is incorrect. We keep adding more mac
addresses to this data structure. The CRC was at the end. The offset 0xCC was
correct.
York
On Jul 12, 2012, at 2:46 PM, Timur Tabi wrote:
The NXID v1 EEPROM format has the CRC at offset 0xFC, but for
On Jul 12, 2012, at 3:37 PM, Scott Wood wrote:
On 07/12/2012 05:03 PM, sun york-R58495 wrote:
Timur,
That patch itself is OK. But the comment is incorrect. We keep adding more
mac addresses to this data structure. The CRC was at the end. The offset
0xCC was correct.
Is there anything
On Jul 12, 2012, at 9:30 PM, Wolfgang Denk wrote:
Dear York,
In message 9f5356fb-8ca2-44de-9089-64abd82ca...@freescale.com you wrote:
That patch itself is OK. But the comment is incorrect. We keep
adding more mac addresses to this data structure. The CRC was at the
end. The offset 0xCC
From: Ira W. Snyder [i...@ovro.caltech.edu]
Sent: Monday, November 21, 2011 10:59 AM
To: u-boot@lists.denx.de
Cc: sun york-R58495
Subject: [PATCH v4 2/3] mpc8xxx: assume unregistered DIMM for invalid SPD
module_type
The generic Freescale DDR SDRAM SPD
Wolfgang,
Without progress indicator, slowe test on memory takes minutes and it looks
like hanging. You probably don't want to run it every time the board boots up.
York Sun
- Original Message -
From:Wolfgang Denk w...@denx.de
To:York Sun york...@freescale.com
Cc:u-boot@lists.denx.de
Wolfgang,
As Timur pointed out, the post framework doesn't work for us. After U-boot
relocate itself to RAM, we have only 2GB memory to test. The best place is
before relocation. Many other boards do that. Following your idea of reusing
code, I can only reuse the test pattern generator. I am
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