[PATCH v3 1/1] usb: dwc2: Fix the write to W1C fields in HPRT register

From: Teik Heng Chong Fix the write to the HPRT register which treat W1C fields as if they were mere RW. This leads to unintended clearing of such fields This bug was found during the testing on Simics model. Referring to specification DesignWare Cores USB 2.0 Hi-Speed On-The-Go (OTG) Databook

[PATCH v2 1/1] usb: dwc2: Fix the write to W1C fields in HPRT register

From: Teik Heng Chong Fix the write to the HPRT register which treat W1C fields as if they were mere RW. This leads to unintended clearing of such fields Signed-off-by: Teik Heng Chong --- V1->V2 - update subject tags to usb:dwc2 --- drivers/usb/host/dwc2.c |

[PATCH] drivers: usb: host: Fix the write to W1C fields in HPRT register

From: Teik Heng Chong Fix the write to the HPRT register which treat W1C fields as if they were mere RW. This leads to unintended clearing of such fields Signed-off-by: Teik Heng Chong --- drivers/usb/host/dwc2.c | 34 -- drivers/usb/host/dwc2.h | 4 2

[PATCH] ARM: socfpga: Ensure FPGA in user mode before enabling the bridges

From: Tien Fong Chee Unexpected behavior and error can occur if FPGA is accessed in unknown state.Always checking with FPGA in user mode is required to ensure system stability. Signed-off-by: Tien Fong Chee Signed-off-by: Teik Heng Chong --- arch/arm/mach-socfpga/misc_arria10.c | 13

[PATCH] configs: socfpga: Add CONFIG_NET_RANDOM_ETHADDR=y to SOCFPGA defconfig

From: Tien Fong Chee Ethernet initialization is only work with properly set MAC addresses. Hence, this config is required to create the random MAC addresses for Ethernet initialization. Signed-off-by: Tien Fong Chee Signed-off-by: Teik Heng Chong --- configs/socfpga_arria10_defconfig | 1

[PATCH] arm: socfpga: switching watchdog 0 to watchdog 1

From: Tien Fong Chee Switching to watchdog 1, because there is a hardware bug found in watchdog 0, it cannot reliable trigger a reset to the CPU. More details can be referred in : Linux commit "59d94d2ed45d598211feb52566e6a806d17f8a3f" Signed-off-by: Tien Fong Chee Signed-off-by:

[PATCH] arm: socfpga: Add watchdog 1 support to A10

From: Tien Fong Chee Add watchdog 1 support to A10, ensure the same enable/disable process as watchdog 0. Signed-off-by: Tien Fong Chee Signed-off-by: Teik Heng Chong --- .../mach-socfpga/include/mach/base_addr_a10.h | 1 + .../include/mach/reset_manager_arria10.h | 1 + arch/arm/mach

[PATCH] arm: socfpga: Remove confusing timer related words from watchdog reset

From: Tien Fong Chee It's confusing to have timer related words along with watchdog reset dessert function, because the function is only release watchdog from reset, so it has no related to any timer setting. Signed-off-by: Tien Fong Chee Signed-off-by: Teik Heng Chong --- arch/arm/mach

[PATCH] ddr: socfpga: Improve A10 SDRAM ECC init function to support watchdog reset

-by: Teik Heng Chong --- drivers/ddr/altera/sdram_arria10.c | 38 ++ 1 file changed, 33 insertions(+), 5 deletions(-) diff --git a/drivers/ddr/altera/sdram_arria10.c b/drivers/ddr/altera/sdram_arria10.c index 4a8f8dea1c..6eb7a34bc0 100644 --- a/drivers/ddr/altera

[PATCH] arm: socfpga: A10: Enable Designware watchdog

Foon Tan Signed-off-by: Teik Heng Chong --- arch/arm/mach-socfpga/Kconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index df44530e83..505d30f9e4 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga

[PATCH] ddr: socfpga: Disable the useeccasdata when ECC is enabled

From: Tien Fong Chee This field allows the FPGA ports to directly access the extra data bits that are normally used to hold the ECC code, so this field must be clear when it's used for ECC data. Signed-off-by: Tien Fong Chee Signed-off-by: Teik Heng Chong --- drivers/ddr/altera/sdram_gen5.c

[PATCH] arm: dts: socfpga: Add dts support for NAND Arria 10 SoCDK

From: Tien Fong Chee Enable dtb build for NAND Arria 10 SoCDK. Signed-off-by: Tien Fong Chee Signed-off-by: Teik Heng Chong --- arch/arm/dts/Makefile | 1 + arch/arm/dts/socfpga_arria10_socdk_nand.dts | 56 ++ .../socfpga_arria10_socdk_nand_handoff.dtsi | 522

[PATCH] HSD #1507500974: configs: arria10: Add bridge enable to CONFIG_BOOTCOMMAND

From: Ley Foon Tan Add "bridge enable" command to CONFIG_BOOTCOMMAND. CONFIG_BOOTCOMMAND="bridge enable;run distro_bootcmd" defconfig is generated from "make savedefconfig". Signed-off-by: Ley Foon Tan Signed-off-by: Teik Heng Chong --- configs/socfpga_ar

[PATCH] ARM: socfpga: Add NAND register address and data register

From: Tien Fong Chee These are required by NAND init in SPL. Signed-off-by: Tien Fong Chee Signed-off-by: Teik Heng Chong --- arch/arm/mach-socfpga/include/mach/base_addr_a10.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_a10.h b/arch

[PATCH] ddr: socfpga: Add ECC DRAM scrubbing support for gen5

and turns them off again. This provides satisfactory performance. Signed-off-by: Tien Fong Chee Signed-off-by: Teik Heng Chong --- arch/arm/mach-socfpga/spl_gen5.c | 4 +++ drivers/ddr/altera/sdram_gen5.c | 57 2 files changed, 61 insertions(+) diff --git

[Update license 1/1] drivers: clk: Update license for Intel N5X device

From: Teik Heng Chong All the source code of clk-mem-n5x.c and clk-n5x.c are from Intel, update the license to use both GPL2.0 and BSD-3 Clause because this copy of code may used for open source and internal project. Signed-off-by: Teik Heng Chong --- drivers/clk/altera/clk-mem-n5x.c | 4