From: Tom Warren
Fix VI_I2C clock source type. Will be needed by VI_I2C driver.
Also added use of INTERNAL_ID macro in two places, needed to keep
the id returned to 8 bits.
Signed-off-by: Tom Warren
---
arch/arm/mach-tegra/tegra210/clock.c | 8
1 file changed, 4 insertions(+), 4
From: JC Kuo
This commit removes the programming sequence that enables PLLE and UPHY
PLL hardware power sequencers. Per TRM, boot software should enable PLLE
and UPHY PLLs in software controlled power-on state and should power
down PLL before jumping into kernel or the next stage boot software.
From: Tom Warren
These patches change some PLL power sequencing, remove pinmuxing
and GPIO init on T210, and adjust some load addresses to allow
for larger kernels.
JC Kuo (1):
t210: do not enable PLLE and UPHY PLL HW PWRSEQ
Tom Warren (2):
t210: Adjust ramdisk_addr_r/fdt_addr_r to allow
From: Tom Warren
The L4T kernel is 32MB+, and can overwrite the ramdisk/fdt loaded
from extlinux.conf. Adjust the load addresses to fix this for now.
Using the calculated_env addresses table from T186 U-Boot is a
better fix, but it isn't working correctly on T210 U-Boot right now,
so this will
From: Tom Warren
T210 CBoot is now doing the full pinmux and GPIO init, based on the DTB
tables. Remove pinmux/GPIO init tables & code from all T210-based builds
below:
p2371-2180 aka TX1
p2371-
e2220-1170
p2571
Signed-off-by: Tom Warren
Acked-by: Stephen Warren
---
From: Tom Warren
This is a WAR for DHCP failure after rebooting from the L4T kernel. The
r8169.c kernel driver is setting bit 19 of the rt816x HW register 0xF0,
which goes by FuncEvent and MISC in various driver source/datasheets.
That bit is called RxDv_Gated_En in the r8169.c kernel driver.
From: Tom Warren
This allows the user to set $serverip in the environment before
executing a DHCP request. If they do, U-Boot will use that IP rather
than using the IP in the DHCP response.
Signed-off-by: Tom Warren
Acked-by: Stephen Warren
---
configs/e2220-1170_defconfig | 1 +
From: Tom Warren
These two patches are from downstream Tegra L4T U-Boot.
Tom Warren (2):
net: rt8169: WAR for DHCP not getting IP after kernel boot/reboot
tegra: Enable CONFIG_BOOTP_PREFER_SERVERIP for all Jetson boards
configs/e2220-1170_defconfig | 1 +
configs/p2371-_defconfig
From: Tom Warren
This Tegra QSPI driver hadn't been brought up to date with how
DM drivers are fetching data from the FDT now, and was pulling
in bogus data for base, max freq, etc. Fixed ofdata_to_platdata
to work the same way it does in the tegra114 SPI driver, using
dev_read_ functions.
From: Tom Warren
claim_bus() is passed a udevice *dev, which is the bus device's parent.
In this driver, claim_bus assumed it was the bus, which caused the
'priv' info pointer to be wrong, and periph_id was incorrect. This in
turn caused the periph clock call to assign the wrong clock (PLLM
From: Tom Warren
These patches fix a couple of problems encountered in the T210 QSPI
driver discovered during Jetson Nano bringup, and adapt the driver to
upstream DM norms.
Tom Warren (3):
qspi: t210: Fix claim_bus's use of the wrong bus/device
qspi: t210: Fix QSPI clock and tap delays
From: Tom Warren
When claim_bus was setting the clock, it reset the QSPI controller,
which wipes out any tap delays set by previous bootloaders (nvtboot,
CBoot for example on Nano). Instead of doing that in claim_bus, which
gets called a lot, moved clock setting to probe(), and set tap delays
From: Tom Warren
As per the T210 TRM, when running at 3.3v, the SDMMC1 tap/trim and
autocal values need to be set to condition the signals correctly before
talking to the SD-card. This is the same as what's being done in CBoot,
but it gets reset when the SDMMC1 HW is soft-reset during SD driver
From: Tom Warren
According to the HW team, for some reason the normal clock select code
picks what appears to be a perfectly valid 375KHz SD card clock, based
on the CAR clock source and SDMMC1 controller register settings (CAR =
408MHz PLLP0 divided by 68 for 6MHz, then a SD Clock Control
From: Tom Warren
These two patches contain fixes for two issues found on T210 MMC during
Nano bringup. Autocal wasn't being done correctly as per the TRM, and
the 375/400KHz MMC card detect clock wasn't using the correct parameters
as per the TRM.
Tom Warren (2):
mmc: t210: Add autocal and
From: Vishruth
U-Boot is configured to build as position independent executable. Enable
relocation of RELA section required to work with different load
addresses.
Signed-off-by: Vishruth
Signed-off-by: Tom Warren
---
configs/p2771--000_defconfig | 1 +
configs/p2771--500_defconfig |
From: Tom Warren
'fdt systemsetup' wasn't working, due to the fact that the 'set' command
was being parsed in do_fdt() by only testing for the leading 's' instead
of "se", which kept the "sys" test further down from executing. Changed
to test for "se" instead, now 'fdt systemsetup' works (to
From: Stephen Warren
This adds to the DT the I2C controllers that connect to the board ID EEPROM,
camera board EEPROM, etc. With this change, you can now probe all I2C devices
on a TX1 board.
Signed-off-by: Tom Warren
---
arch/arm/dts/tegra210-p2371-2180.dts | 18 ++
1 file
From: Tom Warren
These fixes originated on our downstream L4T U-Boot, and include
fdt, pll and code relocation changes.
Stephen Warren (1):
ARM: tegra: p2371-2180: add I2C nodes to DT
Tom Warren (1):
fdt: Fix 'system' command
Vishruth (1):
ARM: tegra: p2771-: enable PIE relocation
From: Tom Warren
Add Macronix MX25U3235F flash device description.
This is a 4MiB part.
Signed-off-by: Tom Warren
---
drivers/mtd/spi/spi-nor-ids.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
index 973b6f8..abdf560 100644
From: Tom Warren
The Jetson Nano Developer Kit is a Tegra X1-based development board. It
is similar to Jetson TX1 but it is not pin compatible. It features 4GB
of LPDDR4, a SPI NOR flash for early boot firmware and an SD card slot
used for storage.
HDMI 2.0 or DP 1.2 are available for display,
21 matches
Mail list logo
