Re: [PATCH] ARM: stm32: Power cycle Buck3 in reset on DHSOM

2023-10-11 Thread Marek Vasut
On 8/16/23 15:28, Marek Vasut wrote: On 8/16/23 15:22, Patrice CHOTARD wrote: On 7/10/23 23:43, Marek Vasut wrote: On 6/17/23 02:36, Marek Vasut wrote: On 6/16/23 15:04, Patrick DELAUNAY wrote: Hi, Hi, [   39.426015] Disabling non-boot CPUs ... [   39.448635] Retrying again to check

Re: [PATCH] ARM: stm32: Power cycle Buck3 in reset on DHSOM

2023-08-16 Thread Marek Vasut
On 8/16/23 15:22, Patrice CHOTARD wrote: On 7/10/23 23:43, Marek Vasut wrote: On 6/17/23 02:36, Marek Vasut wrote: On 6/16/23 15:04, Patrick DELAUNAY wrote: Hi, Hi, [   39.426015] Disabling non-boot CPUs ... [   39.448635] Retrying again to check for CPU kill [   39.451909] CPU1 killed.

Re: [PATCH] ARM: stm32: Power cycle Buck3 in reset on DHSOM

2023-08-16 Thread Patrice CHOTARD
On 7/10/23 23:43, Marek Vasut wrote: > On 6/17/23 02:36, Marek Vasut wrote: >> On 6/16/23 15:04, Patrick DELAUNAY wrote: >>> Hi, >> >> Hi, >> [   39.426015] Disabling non-boot CPUs ... [   39.448635] Retrying again to check for CPU kill [   39.451909] CPU1 killed. U-Boot SPL

Re: [PATCH] ARM: stm32: Power cycle Buck3 in reset on DHSOM

2023-07-10 Thread Marek Vasut
On 7/4/23 23:55, Marek Vasut wrote: On 5/18/23 00:02, Marek Vasut wrote: In case the DHSOM is in suspend state and either reset button is pushed or IWDG2 triggers a watchdog reset, then DRAM initialization could fail as follows:    "    RAM: DDR3L 32bits 2x4Gb 533MHz    DDR invalid size : 0x4,

Re: [PATCH] ARM: stm32: Power cycle Buck3 in reset on DHSOM

2023-07-10 Thread Marek Vasut
On 6/17/23 02:36, Marek Vasut wrote: On 6/16/23 15:04, Patrick DELAUNAY wrote: Hi, Hi, [   39.426015] Disabling non-boot CPUs ... [   39.448635] Retrying again to check for CPU kill [   39.451909] CPU1 killed. U-Boot SPL 2023.07-rc4-8-g2f4664f5c3e (Jun 15 2023 - 08:36:52 +0200) RAM:

Re: [PATCH] ARM: stm32: Power cycle Buck3 in reset on DHSOM

2023-07-04 Thread Marek Vasut
On 5/18/23 00:02, Marek Vasut wrote: In case the DHSOM is in suspend state and either reset button is pushed or IWDG2 triggers a watchdog reset, then DRAM initialization could fail as follows: " RAM: DDR3L 32bits 2x4Gb 533MHz DDR invalid size : 0x4, expected 0x4000 DRAM init

Re: [PATCH] ARM: stm32: Power cycle Buck3 in reset on DHSOM

2023-06-16 Thread Marek Vasut
On 6/16/23 15:04, Patrick DELAUNAY wrote: Hi, Hi, [   39.426015] Disabling non-boot CPUs ... [   39.448635] Retrying again to check for CPU kill [   39.451909] CPU1 killed. U-Boot SPL 2023.07-rc4-8-g2f4664f5c3e (Jun 15 2023 - 08:36:52 +0200) RAM: DDR3-DDR3L 32bits 533000kHz DDR invalid

Re: [PATCH] ARM: stm32: Power cycle Buck3 in reset on DHSOM

2023-06-16 Thread Patrick DELAUNAY
Hi, On 6/15/23 08:44, Marek Vasut wrote: On 5/29/23 03:57, Marek Vasut wrote: Hello again, [...] So the backup domain is loosed on ST board with STPMIC1 only when the power is removed and not for reset or for power off. Thank you for the clarification. I should check suspend/resume on

Re: [PATCH] ARM: stm32: Power cycle Buck3 in reset on DHSOM

2023-06-15 Thread Marek Vasut
On 5/29/23 03:57, Marek Vasut wrote: Hello again, [...] So the backup domain is loosed on ST board with STPMIC1 only when the power is removed and not for reset or for power off. Thank you for the clarification. I should check suspend/resume on EV1 soon ... We do have this problem on

Re: [PATCH] ARM: stm32: Power cycle Buck3 in reset on DHSOM

2023-05-28 Thread Marek Vasut
On 5/25/23 10:08, Patrick DELAUNAY wrote: Hi Marek, Hello Patrick, sorry for the abysmal delay. On 5/18/23 00:02, Marek Vasut wrote: In case the DHSOM is in suspend state and either reset button is pushed or IWDG2 triggers a watchdog reset, then DRAM initialization could fail as follows:  

Re: [PATCH] ARM: stm32: Power cycle Buck3 in reset on DHSOM

2023-05-25 Thread Patrick DELAUNAY
Hi Marek, On 5/18/23 00:02, Marek Vasut wrote: In case the DHSOM is in suspend state and either reset button is pushed or IWDG2 triggers a watchdog reset, then DRAM initialization could fail as follows: " RAM: DDR3L 32bits 2x4Gb 533MHz DDR invalid size : 0x4, expected 0x4000

[PATCH] ARM: stm32: Power cycle Buck3 in reset on DHSOM

2023-05-17 Thread Marek Vasut
In case the DHSOM is in suspend state and either reset button is pushed or IWDG2 triggers a watchdog reset, then DRAM initialization could fail as follows: " RAM: DDR3L 32bits 2x4Gb 533MHz DDR invalid size : 0x4, expected 0x4000 DRAM init failed: -22 ### ERROR ### Please RESET the