Re: [PATCH] mmc: meson-gx: change clock phase value on AGX SoCs

On 2020-12-15 06:19, Jaehoon Chung wrote: > Hi, > > On 12/15/20 3:58 AM, Neil Armstrong wrote: >> Hi, >> >> On 07/12/2020 18:15, Stefan Agner wrote: >>> Amlogic AGX SoCs seem to have issue communicating with some eMMC >>> devices (in particular with a Micron 128GB eMMC 5.1). The device >>> is

Re: [PATCH] mmc: meson-gx: change clock phase value on AGX SoCs

Hi, On 12/15/20 3:58 AM, Neil Armstrong wrote: > Hi, > > On 07/12/2020 18:15, Stefan Agner wrote: >> Amlogic AGX SoCs seem to have issue communicating with some eMMC >> devices (in particular with a Micron 128GB eMMC 5.1). The device >> is detected with 1-bit bus width, and at higher temperature

Re: [PATCH] mmc: meson-gx: change clock phase value on AGX SoCs

Hi, On 07/12/2020 18:15, Stefan Agner wrote: > Amlogic AGX SoCs seem to have issue communicating with some eMMC > devices (in particular with a Micron 128GB eMMC 5.1). The device > is detected with 1-bit bus width, and at higher temperature loading > pretty much anything from the storage fails:

Re: [PATCH] mmc: meson-gx: change clock phase value on AGX SoCs

Hi, On 12/8/20 2:15 AM, Stefan Agner wrote: > Amlogic AGX SoCs seem to have issue communicating with some eMMC > devices (in particular with a Micron 128GB eMMC 5.1). The device > is detected with 1-bit bus width, and at higher temperature loading > pretty much anything from the storage fails:

[PATCH] mmc: meson-gx: change clock phase value on AGX SoCs

Amlogic AGX SoCs seem to have issue communicating with some eMMC devices (in particular with a Micron 128GB eMMC 5.1). The device is detected with 1-bit bus width, and at higher temperature loading pretty much anything from the storage fails: (e.g. fs_devread read error - block). When phase is