Re: [PATCH] riscv: Fix breakage caused by linker relaxation

> > From: Sean Anderson [mailto:sean...@gmail.com] > > Sent: Wednesday, December 18, 2019 10:36 AM > > To: u-boot@lists.denx.de; Rick Jian-Zhi Chen(陳建志) > > Subject: [PATCH] riscv: Fix breakage caused by linker relaxation > > > > Due to the two-instruction

Re: [PATCH] riscv: Fix breakage caused by linker relaxation

> But I wonder how U-Boot managed to work on RISC-V till today? Hm. I think that linker relaxations may also have been disabled by linking with -pie. When I discovered this bug, I had disabled the flag since I was having a hard time getting my compiler to build with --enable-shared. When

Re: [PATCH] riscv: Fix breakage caused by linker relaxation

On Wed, Dec 18, 2019 at 8:09 PM Sean Anderson wrote: > > Due to the two-instruction sequence needed to access arbitrary memory > locations, the RISC-V linker aggressively optimises memory accesses and > jumps at link-time. This is called "linker relaxation," and is discussed > in this SiFive

[PATCH] riscv: Fix breakage caused by linker relaxation

Due to the two-instruction sequence needed to access arbitrary memory locations, the RISC-V linker aggressively optimises memory accesses and jumps at link-time. This is called "linker relaxation," and is discussed in this SiFive article