Sync the serial nodes of the LX2160A based boards with their
representation in Linux. We also imported the clockgen and sysclk nodes
which are dependencies.
Signed-off-by: Ioana Ciornei <ioana.cior...@nxp.com>
---
arch/arm/dts/fsl-lx2160a-qds.dtsi | 11 ++++++++++-
arch/arm/dts/fsl-lx2160a-rdb.dts | 11 ++++++++++-
arch/arm/dts/fsl-lx2160a.dtsi | 22 +++++++++++++---------
3 files changed, 33 insertions(+), 11 deletions(-)
diff --git a/arch/arm/dts/fsl-lx2160a-qds.dtsi
b/arch/arm/dts/fsl-lx2160a-qds.dtsi
index 6635c5258590..e96605b1b4fb 100644
--- a/arch/arm/dts/fsl-lx2160a-qds.dtsi
+++ b/arch/arm/dts/fsl-lx2160a-qds.dtsi
@@ -2,7 +2,7 @@
/*
* NXP LX2160AQDS common device tree source
*
- * Copyright 2018-2020 NXP
+ * Copyright 2018-2020, 2023 NXP
*
*/
@@ -11,6 +11,7 @@
/ {
aliases {
spi0 = &fspi;
+ serial0 = &uart0;
};
};
@@ -286,3 +287,11 @@
&sata3 {
status = "okay";
};
+
+&uart0 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
diff --git a/arch/arm/dts/fsl-lx2160a-rdb.dts b/arch/arm/dts/fsl-lx2160a-rdb.dts
index 399409776e74..aaa59598bd4c 100644
--- a/arch/arm/dts/fsl-lx2160a-rdb.dts
+++ b/arch/arm/dts/fsl-lx2160a-rdb.dts
@@ -5,7 +5,7 @@
* Author: Priyanka Jain <priyanka.j...@nxp.com>
* Sriram Dash <sriram.d...@nxp.com>
*
- * Copyright 2018 NXP
+ * Copyright 2018, 2023 NXP
*
*/
@@ -18,6 +18,7 @@
compatible = "fsl,lx2160ardb", "fsl,lx2160a";
aliases {
spi0 = &fspi;
+ serial0 = &uart0;
};
};
@@ -137,3 +138,11 @@
&sata3 {
status = "okay";
};
+
+&uart0 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
diff --git a/arch/arm/dts/fsl-lx2160a.dtsi b/arch/arm/dts/fsl-lx2160a.dtsi
index 58a408d2dc34..0b0f317f3056 100644
--- a/arch/arm/dts/fsl-lx2160a.dtsi
+++ b/arch/arm/dts/fsl-lx2160a.dtsi
@@ -2,7 +2,7 @@
/*
* NXP lx2160a SOC common device tree source
*
- * Copyright 2018-2021 NXP
+ * Copyright 2018-2021, 2023 NXP
*
*/
@@ -35,30 +35,34 @@
dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
uart0: serial@21c0000 {
- compatible = "arm,pl011";
+ compatible = "arm,sbsa-uart","arm,pl011";
reg = <0x0 0x21c0000 0x0 0x1000>;
- clocks = <&clockgen 4 0>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ current-speed = <115200>;
status = "disabled";
};
uart1: serial@21d0000 {
- compatible = "arm,pl011";
+ compatible = "arm,sbsa-uart","arm,pl011";
reg = <0x0 0x21d0000 0x0 0x1000>;
- clocks = <&clockgen 4 0>;
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+ current-speed = <115200>;
status = "disabled";
};
uart2: serial@21e0000 {
- compatible = "arm,pl011";
+ compatible = "arm,sbsa-uart","arm,pl011";
reg = <0x0 0x21e0000 0x0 0x1000>;
- clocks = <&clockgen 4 0>;
+ interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
+ current-speed = <115200>;
status = "disabled";
};
uart3: serial@21f0000 {
- compatible = "arm,pl011";
+ compatible = "arm,sbsa-uart","arm,pl011";
reg = <0x0 0x21f0000 0x0 0x1000>;
- clocks = <&clockgen 4 0>;
+ interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+ current-speed = <115200>;
status = "disabled";
};
};
--
2.25.1
