Re: [PATCH 1/3] riscv: timer: Update the sifive clint timer driver to support aclint

y ; Rick Jian-Zhi Chen(陳建志) > > > > Subject: [PATCH 1/3] riscv: timer: Update the sifive clint timer driver to > > support aclint > > > > This RISC-V ACLINT specification [1] defines a set of memory mapped devices > > which provide inter-processor interrupts (

Re: [PATCH 1/3] riscv: timer: Update the sifive clint timer driver to support aclint

Hi Bin, > From: Bin Meng > Sent: Monday, June 12, 2023 3:36 PM > To: u-boot@lists.denx.de > Cc: Anup Patel ; Atish Patra ; > Bin Meng ; Palmer Dabbelt ; Paul > Walmsley ; Rick Jian-Zhi Chen(陳建志) > > Subject: [PATCH 1/3] riscv: timer: Update the sifive clint timer dri

[PATCH 1/3] riscv: timer: Update the sifive clint timer driver to support aclint

This RISC-V ACLINT specification [1] defines a set of memory mapped devices which provide inter-processor interrupts (IPI) and timer functionalities for each HART on a multi-HART RISC-V platform. The RISC-V ACLINT specification is defined to be backward compatible with the SiFive CLINT