Hey Andre,
On 6/7/23 04:45, Andre Przywara wrote:
"syscon" really just means "a bunch of gates where AW didn't know where
else to put them".
The good ol' "kitchen sink" register block, eh? Its lack of clear,
definite purpose is even reflected in the name, because when you think
about it,
On Tue, 6 Jun 2023 23:39:24 -0600
Sam Edwards wrote:
Hi Sam,
> On 6/5/23 05:04, Andre Przywara wrote:
> > Ah, that's a good find, but I think it goes a bit deeper:
> > Just to be clear, "SRAMC" stands for "SRAM controller", not "SRAM memory
> > block C" (which other SoCs have, but indeed not
Howdy Andre,
On 6/5/23 05:04, Andre Przywara wrote:
Ah, that's a good find, but I think it goes a bit deeper:
Just to be clear, "SRAMC" stands for "SRAM controller", not "SRAM memory
block C" (which other SoCs have, but indeed not the D1/T113s). However
we (sort of) have an "SRAM controller",
On Fri, 2 Jun 2023 15:49:56 -0600
Sam Edwards wrote:
Hi Sam,
thanks for taking care and sending patched!
> I believe that some sunxis (ncat2?) lack a SRAMC block,
> as accessing this region results in a data abort.
Ah, that's a good find, but I think it goes a bit deeper:
Just to be clear,
On 6/2/23 23:49, Sam Edwards wrote:
I believe that some sunxis (ncat2?) lack a SRAMC block,
as accessing this region results in a data abort. Checking
that it's non-null before accessing it allows this to be
set to NULL for SoCs where it's not present.
Signed-off-by: Sam Edwards
Could it be
I believe that some sunxis (ncat2?) lack a SRAMC block,
as accessing this region results in a data abort. Checking
that it's non-null before accessing it allows this to be
set to NULL for SoCs where it's not present.
Signed-off-by: Sam Edwards
---
drivers/usb/musb-new/sunxi.c | 16
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