On 16/11/2020 06:21, Lokesh Vutla wrote:
On 10/11/20 2:35 pm, Tero Kristo wrote:
With the new raw register mode access PM drivers, A72 core is not
enabled via ti-sci services, leading into bad usecounts for the core.
This effectively shuts down the A72 core when SPL goes down. Prevent the
On 10/11/20 2:35 pm, Tero Kristo wrote:
> With the new raw register mode access PM drivers, A72 core is not
> enabled via ti-sci services, leading into bad usecounts for the core.
> This effectively shuts down the A72 core when SPL goes down. Prevent the
When you meant SPL that is R5 going
With the new raw register mode access PM drivers, A72 core is not
enabled via ti-sci services, leading into bad usecounts for the core.
This effectively shuts down the A72 core when SPL goes down. Prevent the
problem by force enabling the A72 core once, which increases the use
count.
3 matches
Mail list logo
