Re: [PATCH 2/3] ram: ast2600: Improve ddr4 timing and signal quality

On Fri, Nov 11, 2022 at 03:30:07PM +0800, Dylan Hung wrote: > Adjust the following settings to get better timing and signal quality. > > 1. write DQS/DQ delay > - 1e6e2304[0] > - 1e6e2304[15:8] > > 2. read DQS/DQ delay > - 0x1e6e0298[0] > - 0x1e6e0298[15:8] > > 3. CLK/CA timing > -

RE: [PATCH 2/3] ram: ast2600: Improve ddr4 timing and signal quality

> -Original Message- > From: Dylan Hung > Sent: Friday, November 11, 2022 3:30 PM > To: Ryan Chen ; ChiaWei Wang > ; j...@jms.id.au; Dylan Hung > ; u-boot@lists.denx.de > Cc: BMC-SW > Subject: [PATCH 2/3] ram: ast2600: Improve ddr4 timing and signal quality &

[PATCH 2/3] ram: ast2600: Improve ddr4 timing and signal quality

Adjust the following settings to get better timing and signal quality. 1. write DQS/DQ delay - 1e6e2304[0] - 1e6e2304[15:8] 2. read DQS/DQ delay - 0x1e6e0298[0] - 0x1e6e0298[15:8] 3. CLK/CA timing - 0x1e6e01a8[31] 4. Read and write termination - change RTT_ROM from 40 ohm to 48 ohm (MR1[10:8])