Hi Jerome
On Fri, 20 Dec 2019 at 00:07, Jerome Brunet wrote:
>
> On some SoCs, depending on the boot device, the MMC clock block may be
> left in a weird state by the ROM code, in which no decent clock may be
> provided. Reset the related register to make sure a sane MMC clock is
> ready for the
On 19/12/2019 19:36, Jerome Brunet wrote:
> On some SoCs, depending on the boot device, the MMC clock block may be
> left in a weird state by the ROM code, in which no decent clock may be
> provided. Reset the related register to make sure a sane MMC clock is
> ready for the controller.
>
>
On some SoCs, depending on the boot device, the MMC clock block may be
left in a weird state by the ROM code, in which no decent clock may be
provided. Reset the related register to make sure a sane MMC clock is
ready for the controller.
Signed-off-by: Jerome Brunet
---
drivers/clk/meson/axg.c
3 matches
Mail list logo
