On JZ4730 (and I guess all Ingenic/XBurst cores), the CP0 register 15
doesn't support a selector 1 or, for that matter, any selector and always
behaves as if the selector is zero.
We don't need it anyways, these SoCs have just a single processor core.
Signed-off-by: Lubomir Rintel <lkund...@v3.sk>
---
arch/mips/cpu/start.S | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/mips/cpu/start.S b/arch/mips/cpu/start.S
index d0c412236dd..1402fa3d176 100644
--- a/arch/mips/cpu/start.S
+++ b/arch/mips/cpu/start.S
@@ -136,6 +136,8 @@ reset:
#ifdef CONFIG_ARCH_BMIPS
1: mfc0 t0, CP0_DIAGNOSTIC, 3
and t0, t0, (1 << 31)
+#elif CONFIG_ARCH_JZ47XX
+1: and t0, t0, zero
#else
1: mfc0 t0, CP0_EBASE
and t0, t0, MIPS_EBASE_CPUNUM
--
2.28.0
