This is a MIPS subnotebook built around Ingenic JZ4730 SoC. It is known
by many names, including CPC400 and Letux 400, but the OEM seems to be
Skytone and use the "Alpha 400" designator.
Signed-off-by: Lubomir Rintel <lkund...@v3.sk>
---
arch/mips/mach-jz47xx/Kconfig | 23 ++++++++
board/skytone/alpha400/Kconfig | 60 +++++++++++++++++++
board/skytone/alpha400/Makefile | 3 +
board/skytone/alpha400/alpha400.c | 43 ++++++++++++++
configs/alpha400_nand_defconfig | 11 ++++
include/configs/alpha400.h | 98 +++++++++++++++++++++++++++++++
6 files changed, 238 insertions(+)
create mode 100644 board/skytone/alpha400/Kconfig
create mode 100644 board/skytone/alpha400/Makefile
create mode 100644 board/skytone/alpha400/alpha400.c
create mode 100644 configs/alpha400_nand_defconfig
create mode 100644 include/configs/alpha400.h
diff --git a/arch/mips/mach-jz47xx/Kconfig b/arch/mips/mach-jz47xx/Kconfig
index 6fba38c7363..6a01394d4e3 100644
--- a/arch/mips/mach-jz47xx/Kconfig
+++ b/arch/mips/mach-jz47xx/Kconfig
@@ -50,6 +50,29 @@ config SOC_JZ4780
choice
prompt "Board select"
+config TARGET_JZ4730_ALPHA400
+ bool "Skytone Alpha 400 Mini Notebook"
+ select SOC_JZ4730
+ select CMD_MMC if DISTRO_DEFAULTS
+ select SPL_NAND_BASE if SPL
+ select SPL_NAND_DRIVERS if SPL
+ select SPL_NAND_SIMPLE if SPL
+ select SPL_NAND_SUPPORT if SPL
+ select SYS_NAND_U_BOOT_LOCATIONS
+ imply DISTRO_DEFAULTS
+ imply DM_ETH
+ imply DM_ETH_PHY
+ imply DM_GPIO
+ imply DM_MMC
+ imply DM_MTD
+ imply DM_REGULATOR
+ imply DM_REGULATOR_FIXED
+ imply NET_RANDOM_ETHADDR
+ help
+ Support for a MIPS subnotebook built around Ingenic JZ4730 SoC.
+ It is known by many names, including CPC400 and Letux 400, but
+ the OEM seems to be Skytone and use the "Alpha 400" designator.
+
config TARGET_JZ4780_CI20
bool "Creator CI20 Reference Board"
select SOC_JZ4780
diff --git a/board/skytone/alpha400/Kconfig b/board/skytone/alpha400/Kconfig
new file mode 100644
index 00000000000..a8413826a81
--- /dev/null
+++ b/board/skytone/alpha400/Kconfig
@@ -0,0 +1,60 @@
+if TARGET_JZ4730_ALPHA400
+
+config SYS_BOARD
+ default "alpha400"
+
+config SYS_VENDOR
+ default "skytone"
+
+config SYS_CONFIG_NAME
+ default "alpha400"
+
+config DEFAULT_DEVICE_TREE
+ default "alpha400"
+
+config BUILD_TARGET
+ default "u-boot-with-spl.bin" if SPL
+
+config SYS_NAND_U_BOOT_OFFS
+ default 0x20000
+
+config NR_DRAM_BANKS
+ default 16
+
+config JZ4730_SDRAM_BANK_SIZE
+ default 8
+
+config JZ4730_SDRAM_ROW
+ default 13
+
+config JZ4730_SDRAM_COL
+ default 9
+
+config JZ4730_SDRAM_BANKS_PER_CHIP
+ default 4
+
+config JZ4730_SDRAM_WIDTH
+ default 32
+
+config JZ4730_SDRAM_CAS
+ default 2
+
+config JZ4730_SDRAM_TRAS
+ default 45
+
+config JZ4730_SDRAM_RCD
+ default 20
+
+config JZ4730_SDRAM_TPC
+ default 20
+
+config JZ4730_SDRAM_TRW
+ default 7
+
+config JZ4730_SDRAM_TREF
+ default 7812
+
+config JZ4730_SDRAM_CKS
+ default 64
+
+endif
diff --git a/board/skytone/alpha400/Makefile b/board/skytone/alpha400/Makefile
new file mode 100644
index 00000000000..b892abd88a4
--- /dev/null
+++ b/board/skytone/alpha400/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-y := alpha400.o
diff --git a/board/skytone/alpha400/alpha400.c
b/board/skytone/alpha400/alpha400.c
new file mode 100644
index 00000000000..a05d078a661
--- /dev/null
+++ b/board/skytone/alpha400/alpha400.c
@@ -0,0 +1,43 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2020 Lubomir Rintel <lkund...@v3.sk>
+ *
+ * Skytone Alpha 400 board support routines.
+ */
+
+#include <common.h>
+#include <net.h>
+#include <nand.h>
+#include <asm/global_data.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int mac_read_from_eeprom(void)
+{
+ char ethaddr[ARP_HLEN_ASCII + 1] = { 0, };
+ size_t ethaddr_len = ARP_HLEN_ASCII;
+ int ret;
+
+ nand_init();
+ ret = nand_read(get_nand_dev_by_index(0),
+ 0x00400000, ðaddr_len, (void *)ethaddr);
+ if (ret) {
+ pr_err("Unable to read MAC address from NAND.\n");
+ return 0; /* Not serious enough to fail the boot. */
+ }
+
+ env_set("ethaddr", ethaddr);
+ return ret;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = SZ_128M;
+ return 0;
+}
+
+int checkboard(void)
+{
+ puts("Board: Skytone Alpha 400\n");
+ return 0;
+}
diff --git a/configs/alpha400_nand_defconfig b/configs/alpha400_nand_defconfig
new file mode 100644
index 00000000000..cd2daccc821
--- /dev/null
+++ b/configs/alpha400_nand_defconfig
@@ -0,0 +1,11 @@
+CONFIG_MIPS=y
+CONFIG_ARCH_JZ47XX=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_JFFS2=y
+CONFIG_MTDIDS_DEFAULT="nand0=jz4730-nand.0"
+CONFIG_MTDPARTS_DEFAULT="mtdparts=jz4730-nand.0:1m(bootloader),3m(kernel),1m(mac),5m(mini),1014m(yaffs2),-(extend)"
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+# CONFIG_MMC_HW_PARTITIONING is not set
+CONFIG_NS16550_DYNAMIC=y
+CONFIG_WATCHDOG_TIMEOUT_MSECS=0
diff --git a/include/configs/alpha400.h b/include/configs/alpha400.h
new file mode 100644
index 00000000000..673b42f372f
--- /dev/null
+++ b/include/configs/alpha400.h
@@ -0,0 +1,98 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2020 Lubomir Rintel <lkund...@v3.sk>
+ *
+ * Configuration settings for Skytone Alpha 400 board.
+ */
+
+#ifndef __CONFIG_ALPHA400_H__
+#define __CONFIG_ALPHA400_H__
+
+#include <linux/sizes.h>
+
+#ifndef CONFIG_SPL_BUILD
+#define BOOTENV_DEV_NAND_LEGACY(devtypeu, devtypel, instance) \
+ "bootcmd_" #devtypel #instance "=" \
+ "nboot ${kernel_addr_r} " #instance " 0x100000; bootm\0"
+
+#define BOOTENV_DEV_NAME_NAND_LEGACY(devtypeu, devtypel, instance) \
+ #devtypel #instance " "
+
+#define BOOT_TARGET_DEVICES(func) \
+ func(MMC, mmc, 0) \
+ func(NAND_LEGACY, nand, 0)
+
+#include <config_distro_bootcmd.h>
+#endif
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "bootargs=mem=128M console=ttyS0,115200n8 root=/dev/ssfdca1 rw
noatime\0" \
+ "kernel_addr_r=0x80600000\0" \
+ "scriptaddr=0x81000000\0" \
+ "fdt_addr_r=0x81100000\0" \
+ "ramdisk_addr_r=0x81200000\0" \
+ BOOTENV
+
+#define CONFIG_SYS_MALLOC_LEN SZ_16M
+#define CONFIG_SYS_SDRAM_BASE 0x80000000
+#define CONFIG_SYS_INIT_SP_OFFSET 0x00400000
+#define CONFIG_SYS_INIT_SP_ADDR 0x80004000
+#define CONFIG_SYS_LOAD_ADDR 0x81000000
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
+
+#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_NAND_U_BOOT_SIZE SZ_512K
+
+#define CONFIG_SPL_MAX_SIZE SZ_4K
+#define CONFIG_SPL_BSS_MAX_SIZE SZ_4K
+#define CONFIG_SPL_PAD_TO 0x00020000
+#define CONFIG_SPL_BSS_START_ADDR 0x80001000
+#define CONFIG_SPL_STACK 0x80004000
+
+#define CONFIG_SPL_NAND_LOAD
+#define CONFIG_SPL_NAND_RAW_ONLY
+
+/*
+ * NAND flash.
+ */
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_SYS_NAND_MAX_CHIPS 2
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_BASE 0xb4000000
+#define CONFIG_SYS_NAND_PAGE_SIZE SZ_2K
+#define CONFIG_SYS_NAND_BLOCK_SIZE SZ_128K
+#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
+ CONFIG_SYS_NAND_PAGE_SIZE)
+#define CONFIG_SYS_NAND_OOBSIZE 64
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
+
+/*
+ * The MAC address is in a NAND flash partition.
+ */
+#define CONFIG_ID_EEPROM
+#define CONFIG_SYS_RX_ETH_BUFFER 16
+
+/*
+ * The "recovery" partition.
+ */
+#define CONFIG_JFFS2_NAND
+#define CONFIG_JFFS2_DEV "nand0"
+#define CONFIG_JFFS2_PART_OFFSET 0x00500000
+#define CONFIG_JFFS2_PART_SIZE 0x00500000
+
+/*
+ * Useful for SPL.
+ */
+#define CONFIG_CPU_FREQ_HZ 336000000
+#define CONFIG_SYS_CLK 3686400
+
+/*
+ * These are only useful for CONFIG_DEBUG_UART.
+ * The regular serial driver gets its params from DT.
+ */
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_CLK
+#define CONFIG_SYS_NS16550_COM1 0xb0030000
+
+#endif /* __CONFIG_ALPHA400_H__ */
--
2.28.0
