Re: [PATCH u-boot-marvell] ddr: marvell: a38x: Fix Synchronous vs Asynchronous mode determination

2022-01-14 Thread Stefan Roese
On 1/4/22 15:57, Marek Behún wrote: From: Marek Behún Before commit 4c289425752f ("mv_ddr: a38x: add support for ddr async mode"), Asynchornous Mode was only used when the CPU Subsystem Clock Options[4:0] field in the SAR1 register was set to value 0x13: CPU at 2 GHz and DDR at 933 MHz. Then

Re: [PATCH u-boot-marvell] ddr: marvell: a38x: Fix Synchronous vs Asynchronous mode determination

2022-01-05 Thread Stefan Roese
On 1/4/22 15:57, Marek Behún wrote: From: Marek Behún Before commit 4c289425752f ("mv_ddr: a38x: add support for ddr async mode"), Asynchornous Mode was only used when the CPU Subsystem Clock Options[4:0] field in the SAR1 register was set to value 0x13: CPU at 2 GHz and DDR at 933 MHz. Then

Re: [PATCH u-boot-marvell] ddr: marvell: a38x: Fix Synchronous vs Asynchronous mode determination

2022-01-04 Thread Chris Packham
On Wed, Jan 5, 2022 at 3:57 AM Marek Behún wrote: > > From: Marek Behún > > Before commit 4c289425752f ("mv_ddr: a38x: add support for ddr async > mode"), Asynchornous Mode was only used when the CPU Subsystem Clock > Options[4:0] field in the SAR1 register was set to value 0x13: CPU at > 2 GHz

Re: [PATCH u-boot-marvell] ddr: marvell: a38x: Fix Synchronous vs Asynchronous mode determination

2022-01-04 Thread Marek Behún
On Tue, 4 Jan 2022 15:57:49 +0100 Marek Behún wrote: > From: Marek Behún > > Before commit 4c289425752f ("mv_ddr: a38x: add support for ddr async > mode"), Asynchornous Mode was only used when the CPU Subsystem Clock > Options[4:0] field in the SAR1 register was set to value 0x13: CPU at > 2

[PATCH u-boot-marvell] ddr: marvell: a38x: Fix Synchronous vs Asynchronous mode determination

2022-01-04 Thread Marek Behún
From: Marek Behún Before commit 4c289425752f ("mv_ddr: a38x: add support for ddr async mode"), Asynchornous Mode was only used when the CPU Subsystem Clock Options[4:0] field in the SAR1 register was set to value 0x13: CPU at 2 GHz and DDR at 933 MHz. Then commit 4c289425752f ("mv_ddr: a38x: