On Tue, 30 Aug 2022, Pali Rohár wrote:
> > Agreed. But I also understand the reasoning from Maciej, at least in
> > parts. Thinking a bit more about this, my preference would be to still
> > include this workaround per default in U-Boot proper though. To not
> > make things too complicated here.
On Tue, 30 Aug 2022, Stefan Roese wrote:
> > I think I wrote it. One issue is that it is increasing size of SPL image
> > and we really should not include into SPL things which are not required
> > for all target platforms. Lot of boards have size constrained memory
> > requirements and
On Tue, 30 Aug 2022, Pali Rohár wrote:
> > > Moreover this workaround is enabled for all existing hardware and also all
> > > future PCIe hardware, which opens a hole that other PCIe vendors may
> > > introduce same HW issue as on systems where this workaround is required
> > > and
> > > nobody
On Tuesday 30 August 2022 13:15:26 Stefan Roese wrote:
> On 30.08.22 11:19, Pali Rohár wrote:
> > On Tuesday 30 August 2022 10:04:51 Maciej W. Rozycki wrote:
> > > On Sat, 27 Aug 2022, Pali Rohár wrote:
> > >
> > > > Moreover this workaround is enabled for all existing hardware and also
> > > >
On 30.08.22 11:19, Pali Rohár wrote:
On Tuesday 30 August 2022 10:04:51 Maciej W. Rozycki wrote:
On Sat, 27 Aug 2022, Pali Rohár wrote:
Moreover this workaround is enabled for all existing hardware and also all
future PCIe hardware, which opens a hole that other PCIe vendors may
introduce
On Tuesday 30 August 2022 10:04:51 Maciej W. Rozycki wrote:
> On Sat, 27 Aug 2022, Pali Rohár wrote:
>
> > Moreover this workaround is enabled for all existing hardware and also all
> > future PCIe hardware, which opens a hole that other PCIe vendors may
> > introduce same HW issue as on systems
On Sat, 27 Aug 2022, Pali Rohár wrote:
> Moreover this workaround is enabled for all existing hardware and also all
> future PCIe hardware, which opens a hole that other PCIe vendors may
> introduce same HW issue as on systems where this workaround is required and
> nobody would notice it because
On Sat, 27 Aug 2022 at 06:30, Pali Rohár wrote:
>
> PCIe GEN3 link retrain workaround, specially designed for system with PCIe
> ASMedia ASM2824 Switch and other Endpoint devices, unconditionally increase
> size of all SPL binaries with PCIe support, even those which do not require
> it.
>
>
PCIe GEN3 link retrain workaround, specially designed for system with PCIe
ASMedia ASM2824 Switch and other Endpoint devices, unconditionally increase
size of all SPL binaries with PCIe support, even those which do not require it.
Moreover this workaround is enabled for all existing hardware and
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