> From: Peter Yu-Chien Lin(林宇謙)
> Sent: Monday, February 06, 2023 4:11 PM
> To: u-boot@lists.denx.de
> Cc: Leo Yu-Chi Liang(梁育齊) ; Rick Jian-Zhi Chen(陳建志)
> ; prabhakar.cse...@gmail.com; Peter Yu-Chien Lin(林宇謙)
>
> Subject: [PATCH v2 04/10] riscv: cpu: ax25: Simplify
As the OpenSBI v1.2 does not enable the cache [0], we enable
the i/d-cache in harts_early_init() and do not disable in
cleanup_before_linux(). This patch also simplifies the logic
and moves the CSR encoding to include/asm/arch-andes/csr.h.
[0]
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