Re: [PATCH v2 06/10] riscv: ax25: cache.c: Cleanups to L1/L2 cache function used in SPL

> From: Peter Yu-Chien Lin(林宇謙) > Sent: Monday, February 06, 2023 4:11 PM > To: u-boot@lists.denx.de > Cc: Leo Yu-Chi Liang(梁育齊) ; Rick Jian-Zhi Chen(陳建志) > ; prabhakar.cse...@gmail.com; Peter Yu-Chien Lin(林宇謙) > > Subject: [PATCH v2 06/10] riscv: ax25: cache.c: Cl

[PATCH v2 06/10] riscv: ax25: cache.c: Cleanups to L1/L2 cache function used in SPL

This patch refines L1 cache enable/disable and v5l2-cache enable functions. Signed-off-by: Yu Chien Peter Lin Reviewed-by: Leo Yu-Chi Liang --- arch/riscv/cpu/ax25/cache.c | 98 + 1 file changed, 68 insertions(+), 30 deletions(-) diff --git