Re: [PATCH v3 1/7] Revert "riscv: Clear pending interrupts before enabling IPIs"

> Clearing MIP.MSIP is not guaranteed to do anything by the spec. In > addition, most existing RISC-V hardware does nothing when this bit is set. > > The following commits "riscv: Use a valid bit to ignore already-pending > IPIs" and "riscv: Clear pending IPIs on initialization" should implement >

[PATCH v3 1/7] Revert "riscv: Clear pending interrupts before enabling IPIs"

Clearing MIP.MSIP is not guaranteed to do anything by the spec. In addition, most existing RISC-V hardware does nothing when this bit is set. The following commits "riscv: Use a valid bit to ignore already-pending IPIs" and "riscv: Clear pending IPIs on initialization" should implement the origina