dt
> ; Rasmus Villemoes ; Eugen
> Hristev ; Stefan Roese ; Loic
> Poulain ; Peng Fan ; Michal Simek
>
> Cc: u-boot@lists.denx.de; Kautuk Consul ; Anup
> Patel
> Subject: [PATCH v5 2/3] arch/riscv: add semihosting support for RISC-V
>
> We add RISC-V semihosting
On 9/23/22 3:03 AM, Kautuk Consul wrote:
> We add RISC-V semihosting based serial console for JTAG based early
> debugging.
>
> The RISC-V semihosting specification is available at:
> https://github.com/riscv/riscv-semihosting-spec/blob/main/riscv-semihosting-spec.adoc
>
> Signed-off-by: Anup
We add RISC-V semihosting based serial console for JTAG based early
debugging.
The RISC-V semihosting specification is available at:
https://github.com/riscv/riscv-semihosting-spec/blob/main/riscv-semihosting-spec.adoc
Signed-off-by: Anup Patel
Signed-off-by: Kautuk Consul
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arch/riscv/inclu
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