On Sat, Dec 7, 2019 at 12:46 PM Simon Glass wrote:
>
> Most x86 CPUs use a mechanism where the SPI flash is mapped into the very
> top of 32-bit address space, so that it can be executed in place and read
> simply by copying from memory. For an 8MB ROM the mapping starts at
> 0xff80.
>
> Howev
Most x86 CPUs use a mechanism where the SPI flash is mapped into the very
top of 32-bit address space, so that it can be executed in place and read
simply by copying from memory. For an 8MB ROM the mapping starts at
0xff80.
However some recent Intel CPUs do not use a simple 1:1 memory map. Ins
2 matches
Mail list logo
