9, 2020 3:32 AM
> > > > To: u-boot@lists.denx.de
> > > > Cc: Atish Patra; Bin Meng; Anup Patel; Lukas Auer; Heinrich Schuchardt;
> > > > ag...@csgraf.de; ard.biesheu...@linaro.org; Marcus Comstedt; Paul
> > > > Walmsley; Rick Jian-Zhi Chen(陳建志); pa
g; Anup Patel; Lukas Auer; Heinrich Schuchardt;
> > > ag...@csgraf.de; ard.biesheu...@linaro.org; Marcus Comstedt; Paul
> > > Walmsley; Rick Jian-Zhi Chen(陳建志); pal...@dabbelt.com
> > > Subject: [PATCH v6 3/6] riscv: Provide a mechanism to fix DT for reserved
> &
> > ag...@csgraf.de; ard.biesheu...@linaro.org; Marcus Comstedt; Paul Walmsley;
> > Rick Jian-Zhi Chen(陳建志); pal...@dabbelt.com
> > Subject: [PATCH v6 3/6] riscv: Provide a mechanism to fix DT for reserved
> > memory
> >
> > In RISC-V, M-mode software can reserv
> Rick Jian-Zhi Chen(陳建志); pal...@dabbelt.com
> Subject: [PATCH v6 3/6] riscv: Provide a mechanism to fix DT for reserved
> memory
>
> In RISC-V, M-mode software can reserve physical memory regions by setting
> appropriate physical memory protection (PMP) csr. As the PMP csr are
&g
On Sun, Apr 19, 2020 at 3:32 AM Atish Patra wrote:
>
> In RISC-V, M-mode software can reserve physical memory regions
> by setting appropriate physical memory protection (PMP) csr. As the
> PMP csr are accessible only in M-mode, S-mode U-Boot can not read
> this configuration directly. However, M-
In RISC-V, M-mode software can reserve physical memory regions
by setting appropriate physical memory protection (PMP) csr. As the
PMP csr are accessible only in M-mode, S-mode U-Boot can not read
this configuration directly. However, M-mode software can pass this
information via reserved-memory no
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