> From: Bo Gan
> Sent: Monday, June 12, 2023 7:59 AM
> To: u-boot@lists.denx.de
> Cc: Bo Gan ; samin . guo ;
> Yanhong Wang ; Rick Jian-Zhi Chen(陳建志)
> ; Leo Yu-Chi Liang(梁育齊) ; Sean
> Anderson ; Lukasz Majewski
> Subject: [RESEND PATCH v1] arch: riscv: jh711
Background information:
JH7110 SPL runs in L2 LIM (2M in size mapped at 0x800). It
consists of 16 0x2 sized regions, each one can be used as
either L2 cache way or SRAM (not both). From top to bottom, there're
ways 0-15. The way 0 is always enabled, at most 0x1e can be used.
In
2 matches
Mail list logo
