On Thu, Oct 9, 2008 at 1:26 AM, Ed Swarthout <[EMAIL PROTECTED]> wrote:
> This allows a second core to restart without causing a PIC reset.
>
> Internal interupt changes:
> Enable L2 error interrupt IIVPR0 and give it vector 0x100.
> Use correct interrupt (8) for mpc8572 pcie3.
> Add pcie3 interrup
This allows a second core to restart without causing a PIC reset.
Internal interupt changes:
Enable L2 error interrupt IIVPR0 and give it vector 0x100.
Use correct interrupt (8) for mpc8572 pcie3.
Add pcie3 interrupt (11) for mpc8536ds.
Signed-off-by: Ed Swarthout <[EMAIL PROTECTED]>
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cpu/mpc
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