On Tue, Sep 10, 2013 at 11:12 AM, Enric Balletbo i Serra
eballe...@gmail.com wrote:
From: Enric Balletbo i Serra eballe...@iseebcn.com
We can run the DDR at 400MHz, so update the timings for that purpose.
Signed-off-by: Enric Balletbo i Serra eballe...@iseebcn.com
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From: Enric Balletbo i Serra eballe...@iseebcn.com
We can run the DDR at 400MHz, so update the timings for that purpose.
Signed-off-by: Enric Balletbo i Serra eballe...@iseebcn.com
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arch/arm/include/asm/arch-am33xx/ddr_defs.h | 24
board/isee/igep0033/board.c
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