On 22.01.2018 19:54, Daniel Schwierzeck wrote:
>
>
> On 22.01.2018 19:01, Paul Burton wrote:
>> Hi Daniel,
>>
>> On Fri, Jan 19, 2018 at 12:31:25PM +0100, Daniel Schwierzeck wrote:
>>> On 18.01.2018 22:19, Paul Burton wrote:
When constraining the highest DDR address that U-Boot will use fo
On 22.01.2018 19:01, Paul Burton wrote:
> Hi Daniel,
>
> On Fri, Jan 19, 2018 at 12:31:25PM +0100, Daniel Schwierzeck wrote:
>> On 18.01.2018 22:19, Paul Burton wrote:
>>> When constraining the highest DDR address that U-Boot will use for its
>>> data & relocated self, we need to handle the comm
Hi Daniel,
On Fri, Jan 19, 2018 at 12:31:25PM +0100, Daniel Schwierzeck wrote:
> On 18.01.2018 22:19, Paul Burton wrote:
> > When constraining the highest DDR address that U-Boot will use for its
> > data & relocated self, we need to handle the common case in which a 32
> > bit system with 2GB DDR
On 18.01.2018 22:19, Paul Burton wrote:
> When constraining the highest DDR address that U-Boot will use for its
> data & relocated self, we need to handle the common case in which a 32
> bit system with 2GB DDR will have a zero gd->ram_top, due to the
> addition of 2GB (0x8000) to the base a
When constraining the highest DDR address that U-Boot will use for its
data & relocated self, we need to handle the common case in which a 32
bit system with 2GB DDR will have a zero gd->ram_top, due to the
addition of 2GB (0x8000) to the base address of kseg0 (also
0x8000) which overflows
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