The current code uses clrbits_be32 which is incorrect since we are on
a little endian machine here. This patch fixes this issue and also removes
some unnecessary code: Reading the current GPIO bank state is not required
if we are using the SET and CLEAR GPIO registers for setting/clearing
bits.
Signed-off-by: Christian Riesch <christian.rie...@omicron.at>
Cc: Nagabhushana Netagunte <nagabhushana.netagu...@ti.com>
Cc: Rajashekhara, Sudhakar <sudhakar....@ti.com>
---
Hi,
due to lack of hardware I only compile tested this code.
I am looking forward to your comments.
Regards, Christian
board/davinci/da8xxevm/da850evm.c | 14 +++-----------
1 file changed, 3 insertions(+), 11 deletions(-)
diff --git a/board/davinci/da8xxevm/da850evm.c
b/board/davinci/da8xxevm/da850evm.c
index 0c7aabb..147013c 100644
--- a/board/davinci/da8xxevm/da850evm.c
+++ b/board/davinci/da8xxevm/da850evm.c
@@ -335,10 +335,6 @@ int board_early_init_f(void)
int board_init(void)
{
-#if defined(CONFIG_USE_NOR) || defined(CONFIG_DAVINCI_MMC)
- u32 val;
-#endif
-
#ifndef CONFIG_USE_IRQ
irq_init();
#endif
@@ -378,12 +374,10 @@ int board_init(void)
#ifdef CONFIG_USE_NOR
/* Set the GPIO direction as output */
- clrbits_be32((u32 *)GPIO_BANK0_REG_DIR_ADDR, (0x01 << 11));
+ clrbits_le32((u32 *)GPIO_BANK0_REG_DIR_ADDR, (0x01 << 11));
/* Set the output as low */
- val = readl(GPIO_BANK0_REG_SET_ADDR);
- val |= (0x01 << 11);
- writel(val, GPIO_BANK0_REG_CLR_ADDR);
+ writel(0x01 << 11, GPIO_BANK0_REG_CLR_ADDR);
#endif
#ifdef CONFIG_DAVINCI_MMC
@@ -391,9 +385,7 @@ int board_init(void)
clrbits_le32((u32 *)GPIO_BANK0_REG_DIR_ADDR, (0x01 << 11));
/* Set the output as high */
- val = readl(GPIO_BANK0_REG_SET_ADDR);
- val |= (0x01 << 11);
- writel(val, GPIO_BANK0_REG_SET_ADDR);
+ writel(0x01 << 11, GPIO_BANK0_REG_SET_ADDR);
#endif
#ifdef CONFIG_DRIVER_TI_EMAC
--
1.7.9.5
_______________________________________________
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
