On 16-03-18 16:56, David Lechner wrote:
On 03/16/2018 01:26 AM, Mike Looijmans wrote:
On 15-03-18 02:36, David Lechner wrote:
commit 1601dd97edc6 ("davinci: omapl138_lcdk: increase PLL0 frequency")
changed the PLL0 frequency to 456MHz, which is needed for the LCDC IP
block. However, in doing
On Fri, 2018-03-16 at 10:45 -0500, David Lechner wrote:
> On 03/16/2018 04:26 AM, Sekhar Nori wrote:
> > On Thursday 15 March 2018 08:02 PM, David Lechner wrote:
> > >
> > > Thanks for the tips. I've actually done exactly that (using my
> > > own SD
> > > card).
> > >
> > > However, these
On Fri, 2018-03-16 at 10:45 -0500, David Lechner wrote:
> On 03/16/2018 04:26 AM, Sekhar Nori wrote:
> > On Thursday 15 March 2018 08:02 PM, David Lechner wrote:
> > >
> > > Thanks for the tips. I've actually done exactly that (using my
> > > own SD
> > > card).
> > >
> > > However, these
On Wed, 2018-03-14 at 20:36 -0500, David Lechner wrote:
> commit 1601dd97edc6 ("davinci: omapl138_lcdk: increase PLL0
> frequency")
> changed the PLL0 frequency to 456MHz, which is needed for the LCDC IP
> block. However, in doing so, it caused the PLLOUT clock to be outside
> of the allowable
On 03/16/2018 01:26 AM, Mike Looijmans wrote:
On 15-03-18 02:36, David Lechner wrote:
commit 1601dd97edc6 ("davinci: omapl138_lcdk: increase PLL0 frequency")
changed the PLL0 frequency to 456MHz, which is needed for the LCDC IP
block. However, in doing so, it caused the PLLOUT clock to be
On 03/16/2018 04:26 AM, Sekhar Nori wrote:
On Thursday 15 March 2018 08:02 PM, David Lechner wrote:
Thanks for the tips. I've actually done exactly that (using my own SD
card).
However, these changes affect the u-boot SPL image only. I was able to put
the regular u-boot.ais on the SD card,
On Thursday 15 March 2018 08:02 PM, David Lechner wrote:
>
> Thanks for the tips. I've actually done exactly that (using my own SD
> card).
>
> However, these changes affect the u-boot SPL image only. I was able to put
> the regular u-boot.ais on the SD card, but I'm having troubling figuring
>
On Thursday 15 March 2018 08:32 PM, David Lechner wrote:
> On 03/15/2018 09:56 AM, Tom Rini wrote:
>> On Thu, Mar 15, 2018 at 08:01:58PM +0530, Sekhar Nori wrote:
>>> On Thursday 15 March 2018 07:12 PM, Sekhar Nori wrote:
On Thursday 15 March 2018 06:04 PM, Sekhar Nori wrote:
> Thanks for
On Thursday 15 March 2018 08:31 PM, Lokesh Vutla wrote:
>
>
> On Thursday 15 March 2018 08:01 PM, Sekhar Nori wrote:
>> On Thursday 15 March 2018 07:12 PM, Sekhar Nori wrote:
>>> On Thursday 15 March 2018 06:04 PM, Sekhar Nori wrote:
Thanks for the patch and great description. It looks
On 15-03-18 02:36, David Lechner wrote:
commit 1601dd97edc6 ("davinci: omapl138_lcdk: increase PLL0 frequency")
changed the PLL0 frequency to 456MHz, which is needed for the LCDC IP
block. However, in doing so, it caused the PLLOUT clock to be outside
of the allowable specifications given in
On Thursday 15 March 2018 08:01 PM, Sekhar Nori wrote:
> On Thursday 15 March 2018 07:12 PM, Sekhar Nori wrote:
>> On Thursday 15 March 2018 06:04 PM, Sekhar Nori wrote:
>>> Thanks for the patch and great description. It looks correct to me.
>>> Hopefully I can provide some testing feedback too
On 03/15/2018 09:56 AM, Tom Rini wrote:
On Thu, Mar 15, 2018 at 08:01:58PM +0530, Sekhar Nori wrote:
On Thursday 15 March 2018 07:12 PM, Sekhar Nori wrote:
On Thursday 15 March 2018 06:04 PM, Sekhar Nori wrote:
Thanks for the patch and great description. It looks correct to me.
Hopefully I
On Thu, Mar 15, 2018 at 08:01:58PM +0530, Sekhar Nori wrote:
> On Thursday 15 March 2018 07:12 PM, Sekhar Nori wrote:
> > On Thursday 15 March 2018 06:04 PM, Sekhar Nori wrote:
> >> Thanks for the patch and great description. It looks correct to me.
> >> Hopefully I can provide some testing
On Thursday 15 March 2018 07:12 PM, Sekhar Nori wrote:
> On Thursday 15 March 2018 06:04 PM, Sekhar Nori wrote:
>> Thanks for the patch and great description. It looks correct to me.
>> Hopefully I can provide some testing feedback too soon.
>
> Something seems to have broken MMC/SD support on
On 03/15/2018 07:34 AM, Sekhar Nori wrote:
Hi David,
On Thursday 15 March 2018 07:06 AM, David Lechner wrote:
commit 1601dd97edc6 ("davinci: omapl138_lcdk: increase PLL0 frequency")
changed the PLL0 frequency to 456MHz, which is needed for the LCDC IP
block. However, in doing so, it caused the
On Thursday 15 March 2018 06:04 PM, Sekhar Nori wrote:
> Thanks for the patch and great description. It looks correct to me.
> Hopefully I can provide some testing feedback too soon.
Something seems to have broken MMC/SD support on OMAP-L138 LCDK on
2018.03[1]. 2018.01 works fine[2].
Will check
Hi David,
On Thursday 15 March 2018 07:06 AM, David Lechner wrote:
> commit 1601dd97edc6 ("davinci: omapl138_lcdk: increase PLL0 frequency")
> changed the PLL0 frequency to 456MHz, which is needed for the LCDC IP
> block. However, in doing so, it caused the PLLOUT clock to be outside
> of the
On Wed, 2018-03-14 at 20:36 -0500, David Lechner wrote:
> commit 1601dd97edc6 ("davinci: omapl138_lcdk: increase PLL0
> frequency")
> changed the PLL0 frequency to 456MHz, which is needed for the LCDC IP
> block. However, in doing so, it caused the PLLOUT clock to be outside
> of the allowable
commit 1601dd97edc6 ("davinci: omapl138_lcdk: increase PLL0 frequency")
changed the PLL0 frequency to 456MHz, which is needed for the LCDC IP
block. However, in doing so, it caused the PLLOUT clock to be outside
of the allowable specifications given in the OMAP-L138 data sheet. (It
says PLLOUT
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