From: Paul Burton <paul.bur...@imgtec.com>
Add primitive GPIO controller driver for the JZ47xx SoC.
Signed-off-by: Marek Vasut <ma...@denx.de>
Cc: Daniel Schwierzeck <daniel.schwierz...@gmail.com>
Cc: Paul Burton <paul.bur...@imgtec.com>
---
drivers/gpio/Kconfig | 8 +++++
drivers/gpio/Makefile | 1 +
drivers/gpio/gpio-jz47xx.c | 79 ++++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 88 insertions(+)
create mode 100644 drivers/gpio/gpio-jz47xx.c
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 93a7e8c..7140dbe 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -173,4 +173,12 @@ config DM_PCA953X
Now, max 24 bits chips and PCA953X compatible chips are
supported
+
+config JZ47XX_GPIO
+ bool "Ingenic JZ47xx GPIO driver"
+ depends on ARCH_JZ47XX
+ default y
+ help
+ Supports GPIO access on Ingenic JZ47xx SoCs.
+
endmenu
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index ddec1ef..3338517 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -55,3 +55,4 @@ obj-$(CONFIG_PIC32_GPIO) += pic32_gpio.o
obj-$(CONFIG_MVEBU_GPIO) += mvebu_gpio.o
obj-$(CONFIG_MSM_GPIO) += msm_gpio.o
obj-$(CONFIG_PM8916_GPIO) += pm8916_gpio.o
+obj-$(CONFIG_JZ47XX_GPIO) += gpio-jz47xx.o
diff --git a/drivers/gpio/gpio-jz47xx.c b/drivers/gpio/gpio-jz47xx.c
new file mode 100644
index 0000000..7520925
--- /dev/null
+++ b/drivers/gpio/gpio-jz47xx.c
@@ -0,0 +1,79 @@
+/*
+ * Ingenic JZ47xx GPIO
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.va...@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/errno.h>
+#include <asm/io.h>
+#include <mach/jz4780.h>
+
+int gpio_get_value(unsigned gpio)
+{
+ void __iomem *gpio_regs = (void __iomem *)GPIO_BASE;
+ int port = gpio / 32;
+ int pin = gpio % 32;
+
+ return readl(gpio_regs + GPIO_PXPIN(port)) & BIT(pin);
+}
+
+int gpio_set_value(unsigned gpio, int value)
+{
+ void __iomem *gpio_regs = (void __iomem *)GPIO_BASE;
+ int port = gpio / 32;
+ int pin = gpio % 32;
+
+ if (value)
+ writel(BIT(pin), gpio_regs + GPIO_PXPAT0S(port));
+ else
+ writel(BIT(pin), gpio_regs + GPIO_PXPAT0C(port));
+
+ return 0;
+}
+
+int gpio_direction_input(unsigned gpio)
+{
+ void __iomem *gpio_regs = (void __iomem *)GPIO_BASE;
+ int port = gpio / 32;
+ int pin = gpio % 32;
+
+ writel(BIT(pin), gpio_regs + GPIO_PXINTC(port));
+ writel(BIT(pin), gpio_regs + GPIO_PXMASKS(port));
+ writel(BIT(pin), gpio_regs + GPIO_PXPAT1S(port));
+
+ return 0;
+}
+
+int gpio_direction_output(unsigned gpio, int value)
+{
+ void __iomem *gpio_regs = (void __iomem *)GPIO_BASE;
+ int port = gpio / 32;
+ int pin = gpio % 32;
+
+ writel(BIT(pin), gpio_regs + GPIO_PXINTC(port));
+ writel(BIT(pin), gpio_regs + GPIO_PXMASKS(port));
+ writel(BIT(pin), gpio_regs + GPIO_PXPAT1C(port));
+
+ gpio_set_value(gpio, value);
+
+ return 0;
+}
+
+int gpio_request(unsigned gpio, const char *label)
+{
+ int port = gpio / 32;
+
+ if (port >= 6)
+ return -EINVAL;
+
+ return 0;
+}
+
+int gpio_free(unsigned gpio)
+{
+ return 0;
+}
--
2.7.0
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