Re: [U-Boot] [PATCH] iMX6: Disable the L2 before chaning the PL310 latency

2014-09-09 Thread Stefano Babic
On 20/08/2014 11:18, Ye.Li wrote: > From: "Ye.Li" > > The Latency parameters of PL310 Tag RAM latency control register and > Data RAM Latency control register are set in L2 cache enable. And > setting these registers must have PL310 NOT enabled. > > But when using Plugin mode boot, the PL310 is

[U-Boot] [PATCH] iMX6: Disable the L2 before chaning the PL310 latency

2014-08-20 Thread Ye . Li
From: "Ye.Li" The Latency parameters of PL310 Tag RAM latency control register and Data RAM Latency control register are set in L2 cache enable. And setting these registers must have PL310 NOT enabled. But when using Plugin mode boot, the PL310 is enabled by bootrom. The patch disables the PL310

Re: [U-Boot] [PATCH] iMX6: Disable the L2 before chaning the PL310 latency

2014-08-20 Thread Stefano Babic
Hi Ye, On 20/08/2014 11:18, Ye.Li wrote: > From: "Ye.Li" > > The Latency parameters of PL310 Tag RAM latency control register and > Data RAM Latency control register are set in L2 cache enable. And > setting these registers must have PL310 NOT enabled. > > But when using Plugin mode boot, the P