On 4/1/19 8:57 PM, Simon Glass wrote:
> Hi Marek,
>
> On Sat, 30 Mar 2019 at 20:37, Marek Vasut wrote:
>>
>> On 3/30/19 10:18 PM, Simon Glass wrote:
>>> Hi Marek,
>>>
>>> On Sat, 23 Mar 2019 at 11:55, Marek Vasut wrote:
The driver currently calculates the end address of cache flush ope
Hi Marek,
On Sat, 30 Mar 2019 at 20:37, Marek Vasut wrote:
>
> On 3/30/19 10:18 PM, Simon Glass wrote:
> > Hi Marek,
> >
> > On Sat, 23 Mar 2019 at 11:55, Marek Vasut wrote:
> >>
> >> The driver currently calculates the end address of cache flush operation
> >> for the DMA descriptors by adding
On 3/30/19 10:18 PM, Simon Glass wrote:
> Hi Marek,
>
> On Sat, 23 Mar 2019 at 11:55, Marek Vasut wrote:
>>
>> The driver currently calculates the end address of cache flush operation
>> for the DMA descriptors by adding cacheline size to the start address of
>> the last DMA descriptor. This is n
Hi Marek,
On Sat, 23 Mar 2019 at 11:55, Marek Vasut wrote:
>
> The driver currently calculates the end address of cache flush operation
> for the DMA descriptors by adding cacheline size to the start address of
> the last DMA descriptor. This is not safe, as the cacheline size may be,
> in some u
The driver currently calculates the end address of cache flush operation
for the DMA descriptors by adding cacheline size to the start address of
the last DMA descriptor. This is not safe, as the cacheline size may be,
in some unlikely cases, smaller than the DMA descriptor size. Replace the
additi
The driver currently calculates the end address of cache flush operation
for the DMA descriptors by adding cacheline size to the start address of
the last DMA descriptor. This is not safe, as the cacheline size may be,
in some unlikely cases, smaller than the DMA descriptor size. Replace the
additi
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