Hello Scott, Pekon,
On 01/13/2014 07:18 PM, Scott Wood wrote:
The omap_gpmc allows switching ecc at runtime. Since
the NAND_SUBPAGE_READ flag is only set, it is kept when
switching to hw ecc, which is not correct. This leads to
calling chip-ecc.read_subpage which is not a valid
pointer.
On Tue, 2014-01-14 at 21:11 +0100, Jeroen Hofstee wrote:
Hello Scott, Pekon,
On 01/13/2014 07:18 PM, Scott Wood wrote:
The omap_gpmc allows switching ecc at runtime. Since
the NAND_SUBPAGE_READ flag is only set, it is kept when
switching to hw ecc, which is not correct. This leads to
On 01/14/2014 09:21 PM, Scott Wood wrote:
On Tue, 2014-01-14 at 21:11 +0100, Jeroen Hofstee wrote:
Hello Scott, Pekon,
On 01/13/2014 07:18 PM, Scott Wood wrote:
The omap_gpmc allows switching ecc at runtime. Since
the NAND_SUBPAGE_READ flag is only set, it is kept when
switching to hw ecc,
On Tue, 2014-01-14 at 21:38 +0100, Jeroen Hofstee wrote:
On 01/14/2014 09:21 PM, Scott Wood wrote:
All the other cleanup required to change ECC modes is handled by the
OMAP driver; why shouldn't this be as well?
If there are more architectures, who think it is brilliant to switch ecc
it
On 01/14/2014 09:41 PM, Scott Wood wrote:
On Tue, 2014-01-14 at 21:38 +0100, Jeroen Hofstee wrote:
On 01/14/2014 09:21 PM, Scott Wood wrote:
All the other cleanup required to change ECC modes is handled by the
OMAP driver; why shouldn't this be as well?
If there are more architectures, who
On Tue, 2014-01-14 at 21:56 +0100, Jeroen Hofstee wrote:
On 01/14/2014 09:41 PM, Scott Wood wrote:
On Tue, 2014-01-14 at 21:38 +0100, Jeroen Hofstee wrote:
On 01/14/2014 09:21 PM, Scott Wood wrote:
All the other cleanup required to change ECC modes is handled by the
OMAP driver; why
On Tue, 2014-01-14 at 22:15 +0100, Jeroen Hofstee wrote:
On 01/14/2014 10:05 PM, Scott Wood wrote:
I meant a function that resets everything that might have been set
automatically by the previous nand_scan_tail(), not just one flag.
Well I am talking about a single bit bricking my
On 01/14/2014 10:05 PM, Scott Wood wrote:
I meant a function that resets everything that might have been set
automatically by the previous nand_scan_tail(), not just one flag.
Well I am talking about a single bit bricking my board.
Not causing a problem otherwise, besides you falling about
From: Jeroen Hofstee [mailto:jer...@myspectrum.nl]
[...]
The gpmc will fail in hw ecc mode when trying to do subpage reads. Pekon any
suggestion for the elm mode, or should this bit just be cleared
unconditionally?
There are two reasons for not supporting sub-page feature in OMAP platforms:
(1)
Hi Jeroen,
The omap_gpmc allows switching ecc at runtime. Since
the NAND_SUBPAGE_READ flag is only set, it is kept when
switching to hw ecc, which is not correct. This leads to
calling chip-ecc.read_subpage which is not a valid
pointer. Therefore also clear the flag so reading in
hw mode works
Hi Jeroen,
On 01/11/2014 03:39 PM, Jeroen Hofstee wrote:
The omap_gpmc allows switching ecc at runtime. Since
the NAND_SUBPAGE_READ flag is only set, it is kept when
switching to hw ecc, which is not correct. This leads to
calling chip-ecc.read_subpage which is not a valid
pointer. Therefore
The omap_gpmc allows switching ecc at runtime. Since
the NAND_SUBPAGE_READ flag is only set, it is kept when
switching to hw ecc, which is not correct. This leads to
calling chip-ecc.read_subpage which is not a valid
pointer. Therefore also clear the flag so reading in
hw mode works again.
Cc:
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