On Monday, August 03, 2015 at 05:16:29 PM, Dinh Nguyen wrote:
> On 07/27/2015 03:49 PM, Marek Vasut wrote:
> > This series fixes the SPL support on SoCFPGA and cleans up the DDR
> > init code such that it is becoming remotely mainlinable. After this
> > series, the SPL is capable of booting from bo
On 07/27/2015 03:49 PM, Marek Vasut wrote:
> This series fixes the SPL support on SoCFPGA and cleans up the DDR
> init code such that it is becoming remotely mainlinable. After this
> series, the SPL is capable of booting from both SD/MMC and QSPI NOR.
>
> There is still work to be done, but I'd l
On Tuesday, July 28, 2015 at 10:28:39 PM, Pavel Machek wrote:
> Hi!
>
> > > + rw_mgr_mem_load_user(RW_MGR_MRS0_USER_MIRR, RW_MGR_MRS0_USER,
> > > 1);
> > > + /*
> > > +* Need to wait tMOD (12CK or 15ns) time before issuing other
> > > +* commands, but we will have plent
Hi!
> > + rw_mgr_mem_load_user(RW_MGR_MRS0_USER_MIRR, RW_MGR_MRS0_USER,
> > 1);
> > + /*
> > +* Need to wait tMOD (12CK or 15ns) time before issuing other
> > +* commands, but we will have plenty of NIOS cycles before
> > actual
> > +* handoff so its okay.
> > +
On Tuesday, July 28, 2015 at 03:58:34 PM, Pavel Machek wrote:
> On Tue 2015-07-28 15:30:06, Marek Vasut wrote:
> > On Tuesday, July 28, 2015 at 03:13:09 PM, Pavel Machek wrote:
> > > Hi!
> > >
> > > > This series fixes the SPL support on SoCFPGA and cleans up the DDR
> > > > init code such that it
On Tue 2015-07-28 15:30:06, Marek Vasut wrote:
> On Tuesday, July 28, 2015 at 03:13:09 PM, Pavel Machek wrote:
> > Hi!
> >
> > > This series fixes the SPL support on SoCFPGA and cleans up the DDR
> > > init code such that it is becoming remotely mainlinable. After this
> > > series, the SPL is cap
On Tuesday, July 28, 2015 at 03:13:09 PM, Pavel Machek wrote:
> Hi!
>
> > This series fixes the SPL support on SoCFPGA and cleans up the DDR
> > init code such that it is becoming remotely mainlinable. After this
> > series, the SPL is capable of booting from both SD/MMC and QSPI NOR.
> >
> > The
Hi!
> This series fixes the SPL support on SoCFPGA and cleans up the DDR
> init code such that it is becoming remotely mainlinable. After this
> series, the SPL is capable of booting from both SD/MMC and QSPI NOR.
>
> There is still work to be done, but I'd like to start picking it up
> so it can
This series fixes the SPL support on SoCFPGA and cleans up the DDR
init code such that it is becoming remotely mainlinable. After this
series, the SPL is capable of booting from both SD/MMC and QSPI NOR.
There is still work to be done, but I'd like to start picking it up
so it can land in 2015.10
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