On Fri, Jun 21, 2013 at 07:36:09AM +0200, Wolfgang Denk wrote:
Dear ying.zh...@freescale.com,
In message 1371715468-21120-1-git-send-email-ying.zh...@freescale.com you
wrote:
--- a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds
+++ b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds
@@ -1,8 +1,5 @@
On Thu, Jun 27, 2013 at 5:01 PM, Tom Rini tr...@ti.com wrote:
On Fri, Jun 21, 2013 at 07:36:09AM +0200, Wolfgang Denk wrote:
Dear ying.zh...@freescale.com,
In message 1371715468-21120-1-git-send-email-ying.zh...@freescale.com
you wrote:
--- a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds
From: Ying Zhang b40...@freescale.com
For SD/SPI 2-stage bootloader, the On-Chip Rom code loads the SPL into L2 SRAM,
then jump to it to begin execution. After that, the SPL loads the final uboot
image into DDR, then jump to it to begin execution. The segment .resetvec in
the SPL and in final
Dear ying.zh...@freescale.com,
In message 1371715468-21120-1-git-send-email-ying.zh...@freescale.com you
wrote:
--- a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds
+++ b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds
@@ -1,8 +1,5 @@
/*
- * (C) Copyright 2006
- * Wolfgang Denk, DENX Software
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