Hi Bin,
On Sun, 13 Oct 2019 at 19:58, Bin Meng wrote:
>
> Hi Simon,
>
> On Sun, Oct 13, 2019 at 1:53 AM Simon Glass wrote:
> >
> > Hi Bin,
> >
> > On Fri, 11 Oct 2019 at 22:48, Bin Meng wrote:
> > >
> > > Hi Simon,
> > >
> > > On Sat, Oct 12, 2019 at 11:38 AM Simon Glass wrote:
> > > >
> > >
Hi Simon,
On Sun, Oct 13, 2019 at 1:53 AM Simon Glass wrote:
>
> Hi Bin,
>
> On Fri, 11 Oct 2019 at 22:48, Bin Meng wrote:
> >
> > Hi Simon,
> >
> > On Sat, Oct 12, 2019 at 11:38 AM Simon Glass wrote:
> > >
> > > Hi Bin,
> > >
> > > On Thu, 10 Oct 2019 at 03:50, Bin Meng wrote:
> > > >
> > >
Hi Bin,
On Fri, 11 Oct 2019 at 22:48, Bin Meng wrote:
>
> Hi Simon,
>
> On Sat, Oct 12, 2019 at 11:38 AM Simon Glass wrote:
> >
> > Hi Bin,
> >
> > On Thu, 10 Oct 2019 at 03:50, Bin Meng wrote:
> > >
> > > Hi Simon,
> > >
> > > On Wed, Sep 25, 2019 at 10:59 PM Simon Glass wrote:
> > > >
> > >
Hi Simon,
On Sat, Oct 12, 2019 at 11:38 AM Simon Glass wrote:
>
> Hi Bin,
>
> On Thu, 10 Oct 2019 at 03:50, Bin Meng wrote:
> >
> > Hi Simon,
> >
> > On Wed, Sep 25, 2019 at 10:59 PM Simon Glass wrote:
> > >
> > > Newer Intel SoCs have different ways of setting up cache-as-ram (CAR).
> > > Add
Hi Bin,
On Thu, 10 Oct 2019 at 03:50, Bin Meng wrote:
>
> Hi Simon,
>
> On Wed, Sep 25, 2019 at 10:59 PM Simon Glass wrote:
> >
> > Newer Intel SoCs have different ways of setting up cache-as-ram (CAR).
> > Add support for these along with suitable configuration options.
> >
>
> I wonder why do
Hi Simon,
On Wed, Sep 25, 2019 at 10:59 PM Simon Glass wrote:
>
> Newer Intel SoCs have different ways of setting up cache-as-ram (CAR).
> Add support for these along with suitable configuration options.
>
I wonder why do we need do this in U-Boot. Isn't FSP-T doing the CAR for us?
>
Newer Intel SoCs have different ways of setting up cache-as-ram (CAR).
Add support for these along with suitable configuration options.
Signed-off-by: Simon Glass
---
arch/x86/Kconfig| 16 +
arch/x86/cpu/intel_common/Kconfig | 18 +
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