On Thursday 16 November 2017 04:21 PM, Goldschmidt Simon wrote:
> Hi Vignesh,
>
> Vignesh R wrote:
>> [..]
>> Its not actually unaligned access, cadence QSPI IP on TI platforms do
>> not support non-byte accesses except for the last word. As per the TRM:
>> "The external master is only
Hi Vignesh,
Vignesh R wrote:
> [..]
> Its not actually unaligned access, cadence QSPI IP on TI platforms do
> not support non-byte accesses except for the last word. As per the TRM:
> "The external master is only permitted to issue 32-bit data interface
> writes until the last word of an indirect
Hi Simon,
On Thursday 16 November 2017 03:39 PM, Goldschmidt Simon wrote:
[...]
>
> This 32-bit spi transfer mode does not seem to be used too often, all
> other drivers I looked at are transferring byte by byte and thus can
> not be used as an example.
>
> Additionally, the TI platform Vignesh
Simon Goldschmidt wrote:
>Marek Vasut wrote:
>> So what alignment problems do you observe ? If you copy using the CPU
>> only, why do you need the bounce buffer at all ? I don't quite get it.
>
> Sorry for not explaining it good enough:
> I don't observe any alignment problems. mach-socfpga can
Marek Vasut wrote:
> So what alignment problems do you observe ? If you copy using the CPU
> only, why do you need the bounce buffer at all ? I don't quite get it.
Sorry for not explaining it good enough:
I don't observe any alignment problems. mach-socfpga can do unaligned
accesses as well. This
On 11/15/2017 05:18 PM, Goldschmidt Simon wrote:
> Marek Vasut wrote:
>> Why don't you just fix the cache operations in the driver ?
>
> This driver is copying CPU only. There are no cache operations involved!
> Vignesh added the bounce buffer obviously to fix alignment issues on
> his platform.
Marek Vasut wrote:
> Why don't you just fix the cache operations in the driver ?
This driver is copying CPU only. There are no cache operations involved!
Vignesh added the bounce buffer obviously to fix alignment issues on
his platform.
> This bounce-buffer for only CPU operations is just
On 11/15/2017 03:17 PM, Goldschmidt Simon wrote:
> Bounce buffer may be used for CPU-only transfers (this is currently
> the case for cadence_qspi). However, in this case, invalidating the
> data cache might throw away copied data that is still in the cache
> only.
>
> To make CPU-only transfers
Bounce buffer may be used for CPU-only transfers (this is currently
the case for cadence_qspi). However, in this case, invalidating the
data cache might throw away copied data that is still in the cache
only.
To make CPU-only transfers work with bouncebuf (but still take
advantage of having
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