Hi,
On 31-05-16 00:55, Siarhei Siamashka wrote:
On Tue, 31 May 2016 01:48:05 +0300
Siarhei Siamashka wrote:
Currently the AHB1 clock speed is configured as 200MHz by
the SPL, but this causes a subtle and hard to reproduce data
corruption in SRAM C (for example, this can't be easily
detected w
On Tue, 31 May 2016 01:48:05 +0300
Siarhei Siamashka wrote:
> Currently the AHB1 clock speed is configured as 200MHz by
> the SPL, but this causes a subtle and hard to reproduce data
> corruption in SRAM C (for example, this can't be easily
> detected with a trivial memset/memcmp test).
>
> For
Currently the AHB1 clock speed is configured as 200MHz by
the SPL, but this causes a subtle and hard to reproduce data
corruption in SRAM C (for example, this can't be easily
detected with a trivial memset/memcmp test).
For what it's worth, the Allwinner's BSP configures AHB1
as 200MHz, as can be
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