Re: [U-Boot] [PATCH 1/2 V3] arm926: Flush the data cache before disabling it

2012-02-19 Thread Albert ARIBAUD
Hi Christian, Le 18/02/2012 19:51, Christian Riesch a écrit : Hi Albert, On Saturday, February 18, 2012, Albert ARIBAUD wrote: Le 14/01/2012 15:02, Sughosh Ganu a écrit : The current implementation invalidates the cache instead of flushing it. This causes problems on platforms where the spl/

Re: [U-Boot] [PATCH 1/2 V3] arm926: Flush the data cache before disabling it

2012-02-18 Thread Christian Riesch
Hi Albert, On Saturday, February 18, 2012, Albert ARIBAUD wrote: > Le 14/01/2012 15:02, Sughosh Ganu a écrit : >> >> The current implementation invalidates the cache instead of flushing >> it. This causes problems on platforms where the spl/u-boot is already >> loaded to the RAM, with caches enab

Re: [U-Boot] [PATCH 1/2 V3] arm926: Flush the data cache before disabling it

2012-01-14 Thread Albert ARIBAUD
Hi Sughosh Le 14/01/2012 10:21, Sughosh Ganu a écrit : hi Albert, On Sat Jan 14, 2012 at 10:02:16AM +0100, Albert ARIBAUD wrote: /* -* disable MMU stuff and caches +* disable MMU and D cache, and enable I cache. */ mrc p15, 0, r0, c1, c0, 0 -

Re: [U-Boot] [PATCH 1/2 V3] arm926: Flush the data cache before disabling it

2012-01-14 Thread Sughosh Ganu
hi Albert, On Sat Jan 14, 2012 at 10:02:16AM +0100, Albert ARIBAUD wrote: > > /* > >- * disable MMU stuff and caches > >+ * disable MMU and D cache, and enable I cache. > > */ > > mrc p15, 0, r0, c1, c0, 0 > >-bic r0, r0, #0x2300 /* clear bits 13, 9:8 (-

Re: [U-Boot] [PATCH 1/2 V3] arm926: Flush the data cache before disabling it

2012-01-14 Thread Albert ARIBAUD
Hi Sughosh, Le 14/01/2012 08:49, Sughosh Ganu a écrit : The current implementation invalidates the cache instead of flushing it. This causes problems on platforms where the spl/u-boot is already loaded to the RAM, with caches enabled by a first stage bootloader. The V bit of the cp15's control

[U-Boot] [PATCH 1/2 V3] arm926: Flush the data cache before disabling it

2012-01-13 Thread Sughosh Ganu
The current implementation invalidates the cache instead of flushing it. This causes problems on platforms where the spl/u-boot is already loaded to the RAM, with caches enabled by a first stage bootloader. The V bit of the cp15's control register c1 is set to the value of VINITHI on reset. Do not