On 08/20/2015 05:06 PM, Marcel Ziswiler wrote:
On 20 Aug 2015 22:00, Stephen Warren swar...@wwwdotorg.org wrote:
Does the CORE rail get adjusted by DVFS? Hopefully if it does, it is
never set so low that AVP operation at reset is impossible...
Exactly.
+ udelay(1000);
all the
Implement early TPS6586X PMIC rail configuration setting SM0 being
VDD_CORE_1.2V to 1.2 volts and SM1 being VDD_CPU_1.0V to 1.0 volts.
While those are PMIC power-up defaults the SoC might have been reset
separately with certain rails being left at lower DVFS states which
is e.g. the case upon
On 20 Aug 2015 22:00, Stephen Warren swar...@wwwdotorg.org wrote:
Does the CORE rail get adjusted by DVFS? Hopefully if it does, it is
never set so low that AVP operation at reset is impossible...
Exactly.
+ udelay(1000);
all the delays in this patch seem very large. What drove the
On 08/20/2015 01:52 AM, Marcel Ziswiler wrote:
Implement early TPS6586X PMIC rail configuration setting SM0 being
VDD_CORE_1.2V to 1.2 volts and SM1 being VDD_CPU_1.0V to 1.0 volts.
While those are PMIC power-up defaults the SoC might have been reset
separately with certain rails being left at
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