Signed-off-by: Philippe Reynes <trem...@yahoo.fr>
Signed-off-by: Eric Jarrige <eric.jarr...@armadeus.org>
create mode 100644 arch/arm/include/asm/arch-mx27/mxc_nand.h
diff --git a/arch/arm/cpu/arm926ejs/mx27/asm-offsets.c
b/arch/arm/cpu/arm926ejs/mx27/asm-offsets.c
index f3a8d7b..b95c58c 100644
--- a/arch/arm/cpu/arm926ejs/mx27/asm-offsets.c
+++ b/arch/arm/cpu/arm926ejs/mx27/asm-offsets.c
@@ -34,6 +34,7 @@ int main(void)
DEFINE(PCDR1, IMX_PLL_BASE + offsetof(struct pll_regs, pcdr1));
DEFINE(PCCR0, IMX_PLL_BASE + offsetof(struct pll_regs, pccr0));
DEFINE(PCCR1, IMX_PLL_BASE + offsetof(struct pll_regs, pccr1));
+ DEFINE(CCSR, IMX_PLL_BASE + offsetof(struct pll_regs, ccsr));
DEFINE(ESDCTL0_ROF, offsetof(struct esdramc_regs, esdctl0));
DEFINE(ESDCFG0_ROF, offsetof(struct esdramc_regs, esdcfg0));
@@ -41,5 +42,38 @@ int main(void)
DEFINE(ESDCFG1_ROF, offsetof(struct esdramc_regs, esdcfg1));
DEFINE(ESDMISC_ROF, offsetof(struct esdramc_regs, esdmisc));
+ DEFINE(GPCR, IMX_SYSTEM_CTL_BASE +
+ offsetof(struct system_control_regs, gpcr));
+ DEFINE(FMCR, IMX_SYSTEM_CTL_BASE +
+ offsetof(struct system_control_regs, fmcr));
+ DEFINE(DSCR2, IMX_SYSTEM_CTL_BASE +
+ offsetof(struct system_control_regs, dscr2));
+ DEFINE(DSCR3, IMX_SYSTEM_CTL_BASE +
+ offsetof(struct system_control_regs, dscr3));
+ DEFINE(DSCR7, IMX_SYSTEM_CTL_BASE +
+ offsetof(struct system_control_regs, dscr7));
+ DEFINE(DSCR10, IMX_SYSTEM_CTL_BASE +
+ offsetof(struct system_control_regs, dscr10));
+
+ DEFINE(CS0U, IMX_WEIM_BASE + offsetof(struct weim_regs, cs0u));
+ DEFINE(CS0L, IMX_WEIM_BASE + offsetof(struct weim_regs, cs0l));
+ DEFINE(CS0A, IMX_WEIM_BASE + offsetof(struct weim_regs, cs0a));
+ DEFINE(CS1U, IMX_WEIM_BASE + offsetof(struct weim_regs, cs1u));
+ DEFINE(CS1L, IMX_WEIM_BASE + offsetof(struct weim_regs, cs1l));
+ DEFINE(CS1A, IMX_WEIM_BASE + offsetof(struct weim_regs, cs1a));
+ DEFINE(CS2U, IMX_WEIM_BASE + offsetof(struct weim_regs, cs2u));
+ DEFINE(CS2L, IMX_WEIM_BASE + offsetof(struct weim_regs, cs2l));
+ DEFINE(CS2A, IMX_WEIM_BASE + offsetof(struct weim_regs, cs2a));
+ DEFINE(CS3U, IMX_WEIM_BASE + offsetof(struct weim_regs, cs3u));
+ DEFINE(CS3L, IMX_WEIM_BASE + offsetof(struct weim_regs, cs3l));
+ DEFINE(CS3A, IMX_WEIM_BASE + offsetof(struct weim_regs, cs3a));
+ DEFINE(CS4U, IMX_WEIM_BASE + offsetof(struct weim_regs, cs4u));
+ DEFINE(CS4L, IMX_WEIM_BASE + offsetof(struct weim_regs, cs4l));
+ DEFINE(CS4A, IMX_WEIM_BASE + offsetof(struct weim_regs, cs4a));
+ DEFINE(CS5U, IMX_WEIM_BASE + offsetof(struct weim_regs, cs5u));
+ DEFINE(CS5L, IMX_WEIM_BASE + offsetof(struct weim_regs, cs5l));
+ DEFINE(CS5A, IMX_WEIM_BASE + offsetof(struct weim_regs, cs5a));
+ DEFINE(EIM, IMX_WEIM_BASE + offsetof(struct weim_regs, eim));
+
return 0;
}
diff --git a/arch/arm/include/asm/arch-mx27/imx-regs.h
b/arch/arm/include/asm/arch-mx27/imx-regs.h
index 2f6c823..d3a14e1 100644
--- a/arch/arm/include/asm/arch-mx27/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx27/imx-regs.h
@@ -185,7 +185,7 @@ struct iim_regs {
struct fuse_bank {
u32 fuse_regs[0x20];
u32 fuse_rsvd[0xe0];
- } bank[1];
+ } bank[2];
};
struct fuse_bank0_regs {
@@ -511,4 +511,13 @@ struct fuse_bank0_regs {
#define IIM_ERR_SNSE (1 << 2)
#define IIM_ERR_PARITYE (1 << 1)
+/*
+ * Memory areas of the NFC
+ */
+#define IMX_NFC_BASE (0xD8000000)
+#define IMX_NFC_MAIN_AREA0 (0xD8000000)
+#define IMX_NFC_MAIN_AREA1 (0xD8000200)
+#define IMX_NFC_SPARE_AREA0 (0xD8000800)
+#define IMX_NFC_REGS (0xD8000E00)
+
#endif /* _IMX_REGS_H */
diff --git a/arch/arm/include/asm/arch-mx27/mxc_nand.h
b/arch/arm/include/asm/arch-mx27/mxc_nand.h
new file mode 100644
index 0000000..3429601
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx27/mxc_nand.h
@@ -0,0 +1,83 @@
+/*
+ * (c) 2012 Philippe Reynes <trem...@yahoo.fr>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __MXC_NAND_H
+#define __MXC_NAND_H
+
+/*
+ * NFC registers address offest
+ */
+#define NFC_OFFSET_BUFSIZE (0x00) /* Internal SRAM Size */
+#define NFC_OFFSET_BLCK_ADD_LOCK (0x02) /* NAND Flash Block Address for
+ Lock Check */
+#define NFC_OFFSET_BUF_ADDR (0x04) /* Buffer Number for Page Data
+ Transfer To/From Flash Mem */
+#define NFC_OFFSET_FLASH_ADDR (0x06) /* NAND Flash Address */
+#define NFC_OFFSET_FLASH_CMD (0x08) /* NAND Flash Command */
+#define NFC_OFFSET_CONFIG (0x0A) /* NFC Internal Buffer Lock
+ Control */
+#define NFC_OFFSET_ECC_STATUS_RESULT (0x0C) /* Controller Status/Result of
+ Flash Operation */
+#define NFC_OFFSET_ECC_RSLT_MAIN_AREA (0x0E) /* ECC Error Position of Main
+ Area Data Error */
+#define NFC_OFFSET_ECC_RSLT_SPARE_AREA (0x10) /* ECC Error Position of Spare
+ Area Data Error */
+#define NFC_OFFSET_WRPROT (0x12) /* Nand Flash Write Protection */
+#define NFC_OFFSET_UNLOCKSTART_BLKADDR (0x14) /* Start Address for Write
+ Protection Unlock */
+#define NFC_OFFSET_UNLOCKEND_BLKADDR (0x16) /* End Address for Write
+ Protection Unlock */
+#define NFC_OFFSET_WRPR_STAT (0x18) /* Current Nand Flash Write
+ Protection Status */
+#define NFC_OFFSET_CONFIG1 (0x1A) /* Nand Flash Operation
+ Configuration 1 */
+#define NFC_OFFSET_CONFIG2 (0x1C) /* Nand Flash Operation
+ Configuration 2 */
+
+/* NFC_ECC_STATUS_RESULT Status Register Bit Fields */
+#define NFC_ECC_STAT_ERM_SHFT (2) /* ERM shift */
+#define NFC_ECC_STAT_ERS_MASK (0x03) /* ERS mask */
+#define NFC_ECC_STAT_ERROR1 (1<<0) /* correctable error */
+#define NFC_ECC_STAT_ERROR2 (1<<1) /* non correctable error */
+
+/* NFC_CONFIG Control Register Bit Fields */
+#define NFC_CONFIG_UNLOCKED (1<<1) /* unlocked */
+#define NFC_CONFIG_LOCKED (1<<0) /* locked */
+
+/* NFC_CONFIG1 Control Register Bit Fields */
+#define NFC_CONFIG1_CEn (1<<7) /* Flash force CE */
+#define NFC_CONFIG1_RST (1<<6) /* Reset */
+#define NFC_CONFIG1_BIG (1<<5) /* Big Endian Mode */
+#define NFC_CONFIG1_INT_MSK (1<<4) /* Mask Interrupt Bit */
+#define NFC_CONFIG1_ECC_EN (1<<3) /* ECC operation enable */
+#define NFC_CONFIG1_SP_EN (1<<2) /* Flash spare enable */
+
+/* NFC_CONFIG2 Control Register Bit Fields */
+#define NFC_CONFIG2_INT (1<<15) /* Interrupt */
+#define NFC_CONFIG2_FDO_STATUS (4<<3) /* Flash status output */
+#define NFC_CONFIG2_FDO_ID (2<<3) /* Flash ID output */
+#define NFC_CONFIG2_FDO_PAGE (1<<3) /* Flash data output */
+#define NFC_CONFIG2_FDI (1<<2) /* Flash data input */
+#define NFC_CONFIG2_FADD (1<<1) /* Flash address input */
+#define NFC_CONFIG2_FCMD (1<<0) /* Flash command input */
+
+#endif
--
1.7.4.4
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