On Monday, September 15, 2014 at 10:09:34 PM, Dinh Nguyen wrote:
> On 09/15/2014 06:06 AM, Marek Vasut wrote:
[...]
> > + /* get the L4 SP clock which supplied to UART */
> > + reg = readl(&clock_manager_base->main_pll.maindiv);
> > + reg = CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_GET(reg);
> > +
On 09/15/2014 06:06 AM, Marek Vasut wrote:
> From: Pavel Machek
>
> Add the entire bulk of code to read out clock configuration from the SoCFPGA
> CPU registers. This is important for MMC, QSPI and UART drivers as otherwise
> they cannot determine the frequency of their upstream clock.
>
> Signe
From: Pavel Machek
Add the entire bulk of code to read out clock configuration from the SoCFPGA
CPU registers. This is important for MMC, QSPI and UART drivers as otherwise
they cannot determine the frequency of their upstream clock.
Signed-off-by: Pavel Machek
Signed-off-by: Marek Vasut
Cc: C
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