Re: [U-Boot] [PATCH 2/3] MIPS: Split I & D cache line size config

2016-05-31 Thread Daniel Schwierzeck
Am 26.05.2016 um 17:58 schrieb Paul Burton: > Allow L1 Icache & L1 Dcache line size to be specified separately, since > there's no architectural mandate that they be the same. The > [id]cache_line_size functions are tidied up to take advantage of the > fact that the Kconfig entries are always

Re: [U-Boot] [PATCH 2/3] MIPS: Split I & D cache line size config

2016-05-27 Thread Daniel Schwierzeck
Am 26.05.2016 um 18:12 schrieb Marek Vasut: > On 05/26/2016 05:58 PM, Paul Burton wrote: >> Allow L1 Icache & L1 Dcache line size to be specified separately, since >> there's no architectural mandate that they be the same. The >> [id]cache_line_size functions are tidied up to take advantage of

Re: [U-Boot] [PATCH 2/3] MIPS: Split I & D cache line size config

2016-05-26 Thread Marek Vasut
On 05/26/2016 05:58 PM, Paul Burton wrote: > Allow L1 Icache & L1 Dcache line size to be specified separately, since > there's no architectural mandate that they be the same. The > [id]cache_line_size functions are tidied up to take advantage of the > fact that the Kconfig entries are always

[U-Boot] [PATCH 2/3] MIPS: Split I & D cache line size config

2016-05-26 Thread Paul Burton
Allow L1 Icache & L1 Dcache line size to be specified separately, since there's no architectural mandate that they be the same. The [id]cache_line_size functions are tidied up to take advantage of the fact that the Kconfig entries are always present to simply check them for zero rather than