Re: [U-Boot] [PATCH 3/3] ram: k3-am654: Do not rely on default values for certain DDR register

2019-10-25 Thread Tom Rini
On Mon, Oct 07, 2019 at 02:04:27PM +0530, Lokesh Vutla wrote: > From: James Doublesin > > Added the following registers to the DDR configuration: > - ACIOCR0, > - ACIOCR3, > - V2H_CTL_REG, > - DX8SLxDQSCTL. > > Modified enable_dqs_pd and disable_dqs_pd to only touch the associated > bit fields

[U-Boot] [PATCH 3/3] ram: k3-am654: Do not rely on default values for certain DDR register

2019-10-07 Thread Lokesh Vutla
From: James Doublesin Added the following registers to the DDR configuration: - ACIOCR0, - ACIOCR3, - V2H_CTL_REG, - DX8SLxDQSCTL. Modified enable_dqs_pd and disable_dqs_pd to only touch the associated bit fields for pullup and pulldown registers (to preserve slew rate and other bits in that