On Mon, Oct 07, 2019 at 02:04:27PM +0530, Lokesh Vutla wrote:
> From: James Doublesin
>
> Added the following registers to the DDR configuration:
> - ACIOCR0,
> - ACIOCR3,
> - V2H_CTL_REG,
> - DX8SLxDQSCTL.
>
> Modified enable_dqs_pd and disable_dqs_pd to only touch the associated
> bit fields
From: James Doublesin
Added the following registers to the DDR configuration:
- ACIOCR0,
- ACIOCR3,
- V2H_CTL_REG,
- DX8SLxDQSCTL.
Modified enable_dqs_pd and disable_dqs_pd to only touch the associated
bit fields for pullup and pulldown registers (to preserve slew rate and
other bits in that
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