+#define CONFIG_ARMV7_NONSEC
+#define CONFIG_ARMV7_VIRT
+#define CONFIG_SOC_BIG_ENDIAN
+#define CONFIG_DCFG_CCSR_SCRATCHRW1 0x01ee0200
+#define CONFIG_DCFG_CCSR_BRR 0x01ee00e4
Why are you hardcoding the register addresses in this file? I saw that
all registers are
On 07/04/2014 04:48 AM, Xiubo Li-B47053 wrote:
diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h
index d639a6f..f090971 100644
--- a/include/configs/ls1021aqds.h
+++ b/include/configs/ls1021aqds.h
@@ -18,6 +18,15 @@
#define CONFIG_BOARD_EARLY_INIT_F
#define
To enable hypervisors utilizing the ARMv7 virtualization extension
on the LS1021A-QDS/TWR boards with the A7 core tile, we add the
required configuration variable.
Also we define the board specific smp_set_cpu_boot_addr() function to
set the start address for secondary cores in the LS1021A
On 07/03/2014 12:51 PM, Xiubo Li wrote:
To enable hypervisors utilizing the ARMv7 virtualization extension
on the LS1021A-QDS/TWR boards with the A7 core tile, we add the
required configuration variable.
Also we define the board specific smp_set_cpu_boot_addr() function to
set the start address
diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h
index d639a6f..f090971 100644
--- a/include/configs/ls1021aqds.h
+++ b/include/configs/ls1021aqds.h
@@ -18,6 +18,15 @@
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_ARCH_EARLY_INIT_R
+#define
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