On 07/04/2015 03:48 AM, Alexander Stein wrote:
cache flushing addresses must be cacheline size aligned, so mask the
start and stop address appropriately.
As mentioned elsewhere, NAK.
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cache flushing addresses must be cacheline size aligned, so mask the
start and stop address appropriately.
Signed-off-by: Alexander Stein alexander...@web.de
---
arch/arm/cpu/arm1176/cpu.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/cpu/arm1176/cpu.c
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