Re: [U-Boot] [PATCH 3/7] arm: dra7xx: clock: Add the dplls data

2013-02-15 Thread Tom Rini
On Wed, Feb 13, 2013 at 12:59:05PM +0530, Lokesh Vutla wrote: A new DPLL DDR is added in DRA7XX socs. Now clocks to EMIF CD is from DPLL DDR. So DPLL DDR should be locked before initializing RAM. Also adding other dpll data which are different from OMAP5 ES2.0. SYS_CLK running at 20MHz is

[U-Boot] [PATCH 3/7] arm: dra7xx: clock: Add the dplls data

2013-02-12 Thread Lokesh Vutla
A new DPLL DDR is added in DRA7XX socs. Now clocks to EMIF CD is from DPLL DDR. So DPLL DDR should be locked before initializing RAM. Also adding other dpll data which are different from OMAP5 ES2.0. SYS_CLK running at 20MHz is introduced in DRA7xx socs. Signed-off-by: Lokesh Vutla