Re: [U-Boot] [PATCH 6/9] CACHE: nand read/write: Test if start address is aligned

2012-07-06 Thread Aneesh V
On 06/24/2012 05:17 PM, Marek Vasut wrote: This prevents the scenario where data cache is on and the device uses DMA to deploy data. In that case, it might not be possible to flush/invalidate data to RAM properly. The other option is to use bounce buffer, but that involves a lot of copying and th

Re: [U-Boot] [PATCH 6/9] CACHE: nand read/write: Test if start address is aligned

2012-06-26 Thread Marek Vasut
Dear Scott Wood, > On 06/25/2012 08:33 PM, Marek Vasut wrote: > > Dear Scott Wood, > > > >> On 06/25/2012 06:37 PM, Marek Vasut wrote: > >>> Dear Scott Wood, > >>> > On 06/24/2012 07:17 PM, Marek Vasut wrote: > > but that involves a lot of copying and therefore degrades performance > >>

Re: [U-Boot] [PATCH 6/9] CACHE: nand read/write: Test if start address is aligned

2012-06-26 Thread Scott Wood
On 06/25/2012 08:16 PM, Marek Vasut wrote: > Dear Scott Wood, >> Note that in the case of "nand read.oob", depending on NAND page size >> and platform, there's a good chance that you're imposing an alignment >> restriction that is larger than the data being transferred even if the >> user asks to r

Re: [U-Boot] [PATCH 6/9] CACHE: nand read/write: Test if start address is aligned

2012-06-26 Thread Scott Wood
On 06/25/2012 08:33 PM, Marek Vasut wrote: > Dear Scott Wood, > >> On 06/25/2012 06:37 PM, Marek Vasut wrote: >>> Dear Scott Wood, >>> On 06/24/2012 07:17 PM, Marek Vasut wrote: > but that involves a lot of copying and therefore degrades performance > rapidly. Therefore disallow this

Re: [U-Boot] [PATCH 6/9] CACHE: nand read/write: Test if start address is aligned

2012-06-25 Thread Marek Vasut
Dear Scott Wood, > On 06/25/2012 06:37 PM, Marek Vasut wrote: > > Dear Scott Wood, > > > >> On 06/24/2012 07:17 PM, Marek Vasut wrote: > >>> This prevents the scenario where data cache is on and the > >>> device uses DMA to deploy data. In that case, it might not > >>> be possible to flush/invali

Re: [U-Boot] [PATCH 6/9] CACHE: nand read/write: Test if start address is aligned

2012-06-25 Thread Marek Vasut
Dear Scott Wood, > On 06/25/2012 06:42 PM, Marek Vasut wrote: > > Dear Scott Wood, > > > >> On 06/25/2012 03:48 PM, Tom Rini wrote: > >>> Right. What I'm trying to say is it's not a NAND problem it's an > >>> unaligned addresses problem so the solution needs to be easily used > >>> everywhere. >

Re: [U-Boot] [PATCH 6/9] CACHE: nand read/write: Test if start address is aligned

2012-06-25 Thread Scott Wood
On 06/25/2012 06:42 PM, Marek Vasut wrote: > Dear Scott Wood, > >> On 06/25/2012 03:48 PM, Tom Rini wrote: >>> Right. What I'm trying to say is it's not a NAND problem it's an >>> unaligned addresses problem so the solution needs to be easily used >>> everywhere. >> >> OK, so fix it in each drive

Re: [U-Boot] [PATCH 6/9] CACHE: nand read/write: Test if start address is aligned

2012-06-25 Thread Scott Wood
On 06/25/2012 06:37 PM, Marek Vasut wrote: > Dear Scott Wood, > >> On 06/24/2012 07:17 PM, Marek Vasut wrote: >>> This prevents the scenario where data cache is on and the >>> device uses DMA to deploy data. In that case, it might not >>> be possible to flush/invalidate data to RAM properly. The >

Re: [U-Boot] [PATCH 6/9] CACHE: nand read/write: Test if start address is aligned

2012-06-25 Thread Marek Vasut
Dear Scott Wood, > On 06/25/2012 03:48 PM, Tom Rini wrote: > > -BEGIN PGP SIGNED MESSAGE- > > Hash: SHA1 > > > > On 06/25/2012 01:08 PM, Scott Wood wrote: > >> On 06/25/2012 01:43 PM, Tom Rini wrote: > >>> On Mon, Jun 25, 2012 at 11:58:10AM -0500, Scott Wood wrote: > On 06/24/2012 07

Re: [U-Boot] [PATCH 6/9] CACHE: nand read/write: Test if start address is aligned

2012-06-25 Thread Marek Vasut
Dear Tom Rini, > On Mon, Jun 25, 2012 at 11:58:10AM -0500, Scott Wood wrote: > > On 06/24/2012 07:17 PM, Marek Vasut wrote: > > > This prevents the scenario where data cache is on and the > > > device uses DMA to deploy data. In that case, it might not > > > be possible to flush/invalidate data to

Re: [U-Boot] [PATCH 6/9] CACHE: nand read/write: Test if start address is aligned

2012-06-25 Thread Marek Vasut
Dear Scott Wood, > On 06/24/2012 07:17 PM, Marek Vasut wrote: > > This prevents the scenario where data cache is on and the > > device uses DMA to deploy data. In that case, it might not > > be possible to flush/invalidate data to RAM properly. The > > other option is to use bounce buffer, > > Or

Re: [U-Boot] [PATCH 6/9] CACHE: nand read/write: Test if start address is aligned

2012-06-25 Thread Tom Rini
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 On 06/25/2012 02:17 PM, Scott Wood wrote: > On 06/25/2012 03:48 PM, Tom Rini wrote: >> -BEGIN PGP SIGNED MESSAGE- Hash: SHA1 >> >> On 06/25/2012 01:08 PM, Scott Wood wrote: >>> On 06/25/2012 01:43 PM, Tom Rini wrote: On Mon, Jun 25, 2012

Re: [U-Boot] [PATCH 6/9] CACHE: nand read/write: Test if start address is aligned

2012-06-25 Thread Scott Wood
On 06/25/2012 03:48 PM, Tom Rini wrote: > -BEGIN PGP SIGNED MESSAGE- > Hash: SHA1 > > On 06/25/2012 01:08 PM, Scott Wood wrote: >> On 06/25/2012 01:43 PM, Tom Rini wrote: >>> On Mon, Jun 25, 2012 at 11:58:10AM -0500, Scott Wood wrote: On 06/24/2012 07:17 PM, Marek Vasut wrote: > T

Re: [U-Boot] [PATCH 6/9] CACHE: nand read/write: Test if start address is aligned

2012-06-25 Thread Tom Rini
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 On 06/25/2012 01:08 PM, Scott Wood wrote: > On 06/25/2012 01:43 PM, Tom Rini wrote: >> On Mon, Jun 25, 2012 at 11:58:10AM -0500, Scott Wood wrote: >>> On 06/24/2012 07:17 PM, Marek Vasut wrote: This prevents the scenario where data cache is on and

Re: [U-Boot] [PATCH 6/9] CACHE: nand read/write: Test if start address is aligned

2012-06-25 Thread Scott Wood
On 06/25/2012 01:43 PM, Tom Rini wrote: > On Mon, Jun 25, 2012 at 11:58:10AM -0500, Scott Wood wrote: >> On 06/24/2012 07:17 PM, Marek Vasut wrote: >>> This prevents the scenario where data cache is on and the >>> device uses DMA to deploy data. In that case, it might not >>> be possible to flush/i

Re: [U-Boot] [PATCH 6/9] CACHE: nand read/write: Test if start address is aligned

2012-06-25 Thread Tom Rini
On Mon, Jun 25, 2012 at 11:58:10AM -0500, Scott Wood wrote: > On 06/24/2012 07:17 PM, Marek Vasut wrote: > > This prevents the scenario where data cache is on and the > > device uses DMA to deploy data. In that case, it might not > > be possible to flush/invalidate data to RAM properly. The > > oth

Re: [U-Boot] [PATCH 6/9] CACHE: nand read/write: Test if start address is aligned

2012-06-25 Thread Scott Wood
On 06/24/2012 07:17 PM, Marek Vasut wrote: > This prevents the scenario where data cache is on and the > device uses DMA to deploy data. In that case, it might not > be possible to flush/invalidate data to RAM properly. The > other option is to use bounce buffer, Or get cache coherent hardware. :-

[U-Boot] [PATCH 6/9] CACHE: nand read/write: Test if start address is aligned

2012-06-24 Thread Marek Vasut
This prevents the scenario where data cache is on and the device uses DMA to deploy data. In that case, it might not be possible to flush/invalidate data to RAM properly. The other option is to use bounce buffer, but that involves a lot of copying and therefore degrades performance rapidly. Therefo